ITP700 Debug Port Design Guide

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ITP700 Debug Port Design Guide 7
Revision History
Revision Description Revision Date
Rev 1.0 Initial Release with Intel
®
Xeon
™
Processor May 2001
Rev 1.03 Correction of +/- TCLK May 2001
Rev 1.10 Addition of Chapter 5: Intel
®
Pentium
®
4 Processor in the 478 Pin
Package System Implementation Guidelines
Addition of termination information for BPM[5:0]# and Reset# signals
August 2001
Rev 1.15 Append to Chapter 5: Intel
®
Pentium
®
4 Processor in the 478 Pin
Package / Intel
®
Pentium
®
4 Processor with 512KB L2 Cache on 0.13
micron process System Implementation Guidelines
Addition of ITP700 Flex debug port information
Addition of Appendix E: Designer’s Checklist for Schematic and Layout
Reviews
January 2002
Rev 1.20 Addition of Chapter 6: Intel
®
Xeon
™
Processor with 512-KB L2 Cache
at 2.20, 2.0, and 1.80 GHz –DP Server System Implementation
Guidelines
Updated ITP700 Keep-Out Volume Diagram
January 2002
Rev 1.21 Additional explanation of ITP700 Keep-Out Volume changes February 2002
Rev 1.22 Addition to Chapter 5 to include Mobile Intel
®
Pentium
®
4 Processor-M
System Implementation Guidelines
June 2002
Rev 1.30 Chapter 7 added for Intel® Itanium® 2 Processor July 2002
Rev 1.40 Chapter 8 added for Intel® E8870 Chipset August 2002
Rev 1.50 Addition of Intel
®
Xeon
™
Processor MP Server System Implementation
Guidelines
Merge of Chapter 6 with Chapter 4
November 2002
Rev 1.60 Addition to Chapter 7 to include Intel
®
Centrino
™
mobile technology
support
March 2003
Rev 1.65 Append to Chapter 7 to include Intel® Pentium® 4 processor on 90 nm
process System Implementation Guidelines
January 2004