ITP700 Debug Port Design Guide

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ITP700 Debug Port Design Guide
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12 Appendix C – Recovering a
Single-Ended BCLK
The ITP uses a differential ECL receiver to recover the system BCLK. It is possible to modify the
target system hardware to accept a single-ended system clock. This is accomplished through the
creation of a stable reference voltage on the target system. This voltage should equal to the center
of the swing of BCLKn as seen at the debug port. Use relatively low resistance values (such as
200 Ω or less) between the BCLK high-side drive voltage and GND. This will ensure that any
current draw seen on the BCLK pins due to the differential termination of the ITP hardware will
not cause the reference to drift. Include a .01 µF ceramic capacitor to the reference voltage at the
debug port (pin 21) to help keep the voltage reference stable. Note that the required swing of a
single-ended BCLK is effectively double the required swing of the differential clock because of
the nature of a static negative differential reference.