Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.0 Design Guidelines

VRM and EVRD 10.0 Design Guidelines

3 Control Signals

3.1 Output Enable (OUTEN) REQUIRED

The VRM/EVRD should accept an input signal to enable its output voltage. When disabled, the

VRM/EVRD output voltage should go to a high impedance state and should not sink or source

current. When OUTEN is pulled low during the shutdown process, the VRM/EVRD should not

exceed the previous voltage level regardless of the VID setting during the shutdown process.

Once the VRM/EVRD is operating after power-up, it should respond to a deasserted OUTEN

within 500 ms. The circuitry driving OUTEN is an open-collector signal. It is EXPECTED that

the pull-up resistor will be located on the baseboard and will not be integrated into the PWM

controller chip.

Table 3. OUTEN Specifications

Symbol Parameter Min Max Units

Input Voltage High 0.8 3.465 V

Input Voltage Low 0.0 0.400 V

3.2 Voltage Identification (VID[5:0]) REQUIRED

VID [4:0] are compatible with Intel

Pentium

4 and Intel

Xeon™ processors using 5-bit VID

codes. VID [5:0] will be used on processors with 6-bit VID codes.

The VRM/EVRD must accept six lines to set the nominal voltage as defined in this section. When

the VID[4:0] inputs are all high (in this case VID5 is a don’t care), such as when no processor is

installed, the VRM/EVRD should disable its output voltage. If this disable code appears during

previously normal operation, the VRM/EVRD should turn off its output voltage within 500 ms.

The circuitry driving VID[5:0] is an open-collector signal. It is EXPECTED that the pull-up

resistors will be located on the baseboard and will not be integrated into the PWM controller chip.

Other platform components may use VID inputs and may require tighter limits than specified in

Table 4.

A normal no-processor VID [5:0] code for a Vcc regulator will be X11111, where X is defined as

logic 1 or 0, disabling the VRM/EVRD.

Table 4. VID Specifications

Symbol Parameter Min Max Units Notes

Input High Voltage 0.8 3.465 V 1, 2

Input Low Voltage 0 0.4 V 1, 2

NOTES:

1. Other platform components may use VID inputs and may require tighter limits.

2. These specifications are for the VRM/EVRD. They are not processor specifications.