Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.0 Design Guidelines

VRM and EVRD 10.0 Design Guidelines

It is recommended that hysteresis be designed into the thermal sense circuit to prevent a scenario

in which the VR_hot# signal is rapidly being asserted and deasserted.

6.3 Load Indicator Output (Load_current) PROPOSED

The VRM/EVRD may have an output with a voltage level that varies linearly with the

VRM/EVRD output current. The PWM controller supplier may specify a voltage-current

relationship consistent with the controller’s current sensing method. Baseboards may route this

output to a test point for system validation.

6.4 VRM Identification (VRM_ID0, VRM_ID1) PROPOSED

The VRM identification signals must be connected to ground on the VRM10.0 module. These

signals can be used in systems that are designed to accept both VRM10.0 and VRM10.1 modules.

The intent is to provide the system designer with a method to ensure that the capabilities of the

installed VRM match the power requirements of the processor.

These signals correspond to the Load Line Select (LL0, LL1) signals on the VRM10.1 module.

For processors that require VRM 10.1, one or both of these Load Line Select signals will be tied

to a pull-up resistor on the baseboard. If a VRM10.1 module is inserted into the connector, the

signals will be pulled up as expected. However, if a VRM10.0 module is inserted into the

connector, both signals will be low since they are tied to ground on the VRM10.0 module. The

system can then take the appropriate action.

Some SKUs of the Intel® Xeon™ processor with 800 MHz system bus will work with either a

VRM10.0 module or a VRM10.1 module. In this case the VRM identification signals are a don’t

care.

For more information on the Load Line Select signals, see the Voltage Regulator Module (VRM)

and Enterprise Voltage Regulator-Down (EVRD) 10.1 Design Guidelines.