Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.1 Design Guidelines

Output Voltage Requirements
12 Voltage Regulator Module (VRM) and Enterprise Voltage
Regulator-Down (EVRD) 10.1 Design Guidelines
2.4 Processor Vcc Overshoot - REQUIRED
The Intel
®
Xeon™ processor with 800 MHz system bus can tolerate short transient overshoot
events where Vcc exceeds the VID voltage when transitioning from a high-to-low current load
condition. This processor Vcc overshoot does not apply to the 64-bit Intel
®
Xeon™ processor MP.
This overshoot cannot exceed VID + V
OS
_
MAX
. The overshoot duration, which is the time that the
overshoot can remain above VID, cannot exceed T
OS
_
MAX
. These specifications apply to the
processor socket voltage as measured across the remote sense points and should be taken with a
20 MHz bandwidth limited oscilloscope.
• V
OS
_
MAX
= Maximum overshoot voltage above VID = 50 mV
• T
OS
_
MAX
= Maximum overshoot time duration above VID = 25 µs
• Vcc overshoot does not apply to the 64-bit Intel® Xeon™ processor MP.
2.5 Stability - REQUIRED
The VRM/EVRD needs to be unconditionally stable under all specified output voltage ranges,
current transients of any duty cycle, and up to repetition rates of 1 MHz. The VRM/EVRD should
be stable under a no load condition.
2.6 Processor Power Sequencing - REQUIRED
The VRM/EVRD must support platforms with defined power-up sequences. Figure 2-4 shows a
block diagram of a system power-on sequencing implementation, and Figure 2-5 shows a timing
diagram of the power-on sequencing requirements.
Figure 2-3. Processor Vcc Overshoot Example Waveform
0 5 10 15 20 25
Time [us]
Voltage [V]
VID - 0.000
VID + 0.050
V
OS
T
OS
T
OS
: Overshoot time above VID
V
OS
: Overshoot voltage above VID