Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.1 Design Guidelines

Output Voltage Requirements

14 Voltage Regulator Module (VRM) and Enterprise Voltage

Regulator-Down (EVRD) 10.1 Design Guidelines

2.7 Dynamic Voltage Identification (VID) - REQUIRED

VRM/EVRD 10.1 supports dynamic VID across the entire VID table. The VRM/EVRD must be

capable of accepting voltage level changes of 12.5 mV steps every 5 µs, up to 36 steps (450 mV) in

180 µs. The low voltage state will be maintained for at least 50 µs. The worst case settling time,

including line-to-line skew, for the six VID lines is 400 ns. The VID inputs should contain circuitry

to prevent false tripping or latching of VID codes during the settling time.

During a transition, the output voltage must be between the maximum voltage of the high range

(“A” in Figure 2-6) and the minimum voltage of the low range (“B”). The VRM/EVRD must

respond to a transition from VID-low to VID-high by regulating its Vcc output to the range defined

by the new, final VID code within 50 µs of the final step. The time to move the output voltage from

VID-high to VID-low will depend on the PWM controller design, the amount of system decoupling

capacitance, and the processor load.

Figure 2-6 shows operating states as a representative processor changes levels. The diagram

assumes steady state, maximum current during the transition for ease of illustration; actual

processor behavior allows for any dIcc/dt event during the transitions, depending on the code it is

executing at that time. In the example, the processor begins in a high-load condition. In transitions

12 and 23, the processor prepares to switch to the low-voltage range with a transition to a low-load

condition, followed by an increased activity level. Transition 34 is a simplification of the multiple

steps from the high-voltage load line to the low-voltage load line. Transition 45 is an example of a

response to a load change during normal operation in the lower range.

Figure 2-7 is an example of dynamic VID. The diagram in Figure 2-7 assumes steady state,

constant current during the dynamic VID transition for ease of illustration; actual processor

behavior allows for any dIcc/dt during the transitions, depending on the code it is executing at that

time. Note that during dynamic VID, the processor will not output VID codes that would disable

the voltage regulator output voltage.

Figure 2-6. Processor Transition States

VID High Load Line

Icc-max

VID Low Load Line