Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.2 Design Guidelines

Output Voltage Requirements
14 Voltage Regulator Module (VRM) and Enterprise Voltage
Regulator-Down (EVRD) 10.2 Design Guidelines
condition, followed by an increased activity level. Transition 34 is a simplification of the multiple
steps from the high-voltage load line to the low-voltage load line. Transition 45 is an example of a
response to a load change during normal operation in the lower range.
Figure 2-6 is an example of dynamic VID. The diagram in Figure 2-6 assumes steady state,
constant current during the dynamic VID transition for ease of illustration; actual processor
behavior allows for any dIcc/dt during the transitions, depending on the code it is executing at that
time. Note that during dynamic VID, the processor will not output VID codes that would disable
the voltage regulator output voltage.
Figure 2-5. Processor Transition States
VID High Load Line
1
2
3
4
Icc-max
5
VID Low Load Line
A
B
Figure 2-6. Dynamic VID Transition States Illustration
high VID to low VID
Vcc transition
450 mV
50 µs maximum settling
from registering final VID
450 mV
low VID to
high VID
Vcc transition
The diagram assumes steady state, constant current during the dynamic VID.
Transition for ease of illustration; actual processor behavior allows for any dIcc/dt
event during the transitions, depending on the code it is executing at that time.
VID 5
36 VID steps @ 5 µs each step = 180 µs
Maximum Vc
Setting
50 µs maximum settling
from registering final VID
VID 4
VID 3
VID 2
VID 1
VID 0
400 ns
worst case
VID
settling time
Upper equals
Lower equals
Start VID-01.25m
Ω
*Icc - 40mV
Final VID-01.25m
Ω
*Icc
Upper equals
Lower equals
Start VID-01.25m
Ω
Final VID-01.25m
Ω
*Icc - 40mV