Intel Pentium M Processor on 90nm Process with 2-MB L2 Cache Datasheet

4 Datasheet
Figures
2-1 Clock Control States................................................................................................................... 11
3-1 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#A)............................ 31
3-2 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#A) ...................32
3-3 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#B)............................ 33
3-4 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#B) ...................34
3-5 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#C) ...........................35
3-6 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#C) ...................36
3-7 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#D) ...........................37
3-8 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#D) ...................38
3-9 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#E)............................ 39
3-10Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#E) ................... 40
3-11Active VCC and ICC Load Line ..................................................................................................43
3-12Deep Sleep VCC and ICC Load Line .........................................................................................44
4-1 Micro-FCPGA Package Top and Bottom Isometric Views ......................................................... 47
4-2 Micro-FCPGA Package - Top and Side Views ...........................................................................48
4-3 Micro-FCPGA Package - Bottom View....................................................................................... 49
4-4 Micro-FCBGA Package Top and Bottom Isometric Views ......................................................... 51
4-5 Micro-FCBGA Package Top and Side Views .............................................................................52
4-6 Micro-FCBGA Package Bottom View .........................................................................................54
4-7 The Coordinates of the Processor Pins as Viewed from the Top of the Package......................55