Specification Update


Intel
®
Core
™
i5-600, i3-500 Desktop Processor Series and
Intel
®
Pentium Desktop Processor 6000 Series
November 2014 Specification Update
Document Number: 322911-021US 27
AAU30. Reported Memory Type May Not Be Used to Access the VMCS and
Referenced Data Structures
Problem: Bits 53:50 of the IA32_VMX_BASIC MSR report the memory type that the processor
uses to access the VMCS and data structures referenced by pointers in the VMCS. Due
to this erratum, a VMX access to the VMCS or referenced data structures will instead
use the memory type that the MTRRs (memory-type range registers) specify for the
physical address of the access.
Implication: Bits 53:50 of the IA32_VMX_BASIC MSR report that the WB (write-back) memory type
will be used but the processor may use a different memory type.
Workaround: Software should ensure that the VMCS and referenced data structures are located at
physical addresses that are mapped to WB memory type by the MTRRs.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU31. Changing the Memory Type for an In-Use Page Translation May Lead
to Memory-Ordering Violations
Problem: Under complex microarchitectural conditions, if software changes the memory type for
data being actively used and shared by multiple threads without the use of semaphores
or barriers, software may see load operations execute out of order.
Implication: Memory ordering may be violated. Intel has not observed this erratum with any
commercially-available software.
Workaround: Software should ensure pages are not being actively used before requesting their
memory type be changed.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU32. Erratum AAU32 added to this specification Update in error; all erratum
details removed from the specification update document.
AAU33. Delivery of Certain Events Immediately Following a VM Exit May Push
a Corrupted RIP onto the Stack
Problem: If any of the following events is delivered immediately following a VM exit to 64-bit
mode from outside 64-bit mode, bits 63:32 of the RIP value pushed on the stack may
be cleared to 0:
• A non-maskable interrupt (NMI);
• A machine-check exception (#MC);
• A page fault (#PF) during instruction fetch; or
• A general-protection exception (#GP) due to an attempt to decode an instruction
whose length is greater than 15 bytes.
Implication: Unexpected behavior may occur due to the incorrect value of the RIP on the stack.
Specifically, return from the event handler via IRET may encounter an unexpected page
fault or may begin fetching from an unexpected code address.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.