Specification Update

Intel
®
Core
™
i5-600, i3-500 Desktop Processor Series and
Intel
®
Pentium Desktop Processor 6000 Series
Specification Update November 2014
34 Document Number: 322911-021US
AAU52. Performance Monitor Events DCACHE_CACHE_LD and
DCACHE_CACHE_ST May Overcount
Problem: The performance monitor events DCACHE_CACHE_LD (Event 40H) and
DCACHE_CACHE_ST (Event 41H) count cacheable loads and stores that hit the L1
cache. Due to this erratum, in addition to counting the completed loads and stores, the
counter will incorrectly count speculative loads and stores that were aborted prior to
completion.
Implication: The performance monitor events DCACHE_CACHE_LD and DCACHE_CACHE_ST may
reflect a count higher than the actual number of events.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU53. Rapid Core C3/C6 Transitions May Cause Unpredictable System
Behavior
Problem: Under a complex set of internal conditions, cores rapidly performing C3/C6 transitions
in a system with Intel
®
Hyper-Threading Technology enabled may cause a machine
check error (IA32_MCi_STATUS.MCACOD = 0x0106), system hang or unpredictable
system behavior.
Implication: This erratum may cause a machine check error, system hang or unpredictable system
behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU54. APIC Timer CCR May Report 0 in Periodic Mode
Problem: In periodic mode the APIC timer CCR (current-count register) is supposed to be
automatically reloaded from the initial-count register when the count reaches 0,
consequently software would never be able to observe a value of 0. Due to this
erratum, software may read 0 from the CCR when the timer has counted down and is in
the process of re-arming.
Implication: Due to this erratum, an unexpected value of 0 may be read from the APIC timer CCR
when in periodic mode.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU55. Performance Monitor Events INSTR_RETIRED and
MEM_INST_RETIRED May Count Inaccurately
Problem: The performance monitor event INSTR_RETIRED (Event C0H) should count the number
of instructions retired, and MEM_INST_ RETIRED (Event 0BH) should count the number
of load or store instructions retired. However, due to this erratum, they may
undercount.
Implication: The performance monitor event INSTR_RETIRED and MEM_INST_RETIRED may reflect
a count lower than the actual number of events.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.