Specification Update


Intel
®
Core
™
i5-600, i3-500 Desktop Processor Series and
Intel
®
Pentium Desktop Processor 6000 Series
November 2014 Specification Update
Document Number: 322911-021US 43
AAU85. The Combination of a Page-Split Lock Access And Data Accesses That
Are Split Across Cacheline Boundaries May Lead to Processor Livelock
Problem: Under certain complex micro-architectural conditions, the simultaneous occurrence of a
page-split lock and several data accesses that are split across cacheline boundaries
may lead to processor livelock.
Implication: Due to this erratum, a livelock may occur that can only be terminated by a processor
reset. Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU86. Processor Hangs on Package C6 State Exit
Problem: An internal timing condition in the processor power management logic will result in
processor hangs upon a Package C6 state exit.
Implication: Due to this erratum, the processor will hang during Package C6 state exit.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU87. A Synchronous SMI May be Delayed
Problem: A synchronous SMI (System Management Interrupt) occurs as a result of an SMI
generating I/O Write instruction and should be handled prior to the next instruction
executing. Due to this erratum, the processor may not observe the synchronous SMI
prior to execution of the next instruction.
Implication: Due to this erratum, instructions after the I/O Write instruction, which triggered the
SMI, may be allowed to execute before the SMI handler. Delayed delivery of the SMI
may make it difficult for an SMI Handler to determine the source of the SMI. Software
that relies on the IO_SMI bit in SMM save state or synchronous SMI behavior may not
function as expected.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU88. FP Data Operand Pointer May Be Incorrectly Calculated After an FP
Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit
Address Size in 64-bit Mode
Problem: The FP (Floating Point) Data Operand Pointer is the effective address of the operand
associated with the last non-control FP instruction executed by the processor. If an 80-
bit FP access (load or store) uses a 32-bit address size in 64-bit mode and the memory
access wraps a 4-Gbyte boundary and the FP environment is subsequently saved, the
value contained in the FP Data Operand Pointer may be incorrect.
Implication: Due to this erratum, the FP Data Operand Pointer may be incorrect. Wrapping an 80-bit
FP load around a 4-Gbyte boundary in this way is not a normal programming practice.
Intel has not observed this erratum with any commercially available software.
Workaround: If the FP Data Operand Pointer is used in a 64-bit operating system which may run code
accessing 32-bit addresses, care must be taken to ensure that no 80-bit FP accesses
are wrapped around a 4-Gbyte boundary.
Status: For the steppings affected, see the Summary Tables of Changes.