Intel® 80219 General Purpose PCI Processor Specification Update July 2004 Notice: The Intel® 80219 General Purpose PCI Processor (80219) may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update.
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Intel® 80219 General Purpose PCI Processor Contents Revision History ......................................................................................... 5 Preface....................................................................................................... 6 Summary Table of Changes....................................................................... 7 Identification Information...........................................................................11 Core Errata .......................
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Intel® 80219 General Purpose PCI Processor Revision History Revision History Date Version July 2004 002 Added Specification Clarification 7. November 2003 001 Initial Release.
Intel® 80219 General Purpose PCI Processor Preface Preface This document is an update to the specifications contained in the Affected Documents/Related Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools.
Intel® 80219 General Purpose PCI Processor Summary Table of Changes Summary Table of Changes The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the Intel® 80219 General Purpose PCI Processor product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted.
Intel® 80219 General Purpose PCI Processor Summary Table of Changes Core Errata Steppings No. Page Status Errata A-0 8 1 X 13 NoFix Boundary Scan Is Not Fully Compliant to the IEEE 1149.
Intel® 80219 General Purpose PCI Processor Summary Table of Changes Non-Core Errata Steppings No.
Intel® 80219 General Purpose PCI Processor Summary Table of Changes Specification Changes Steppings No. Page Specification Changes A-0 1 X 24 Signal NC2 was renamed to P_BMI (AE23). New function added to signal P_BMI. Specification Clarifications Steppings No. Page Status Specification Clarifications A-0 1 X 26 NoFix The Intel® 80219 general purpose PCI processor is compliant with the PCI Local Bus Specification, Revision 2.
Intel® 80219 General Purpose PCI Processor Identification Information Identification Information Markings Figure 1.
Intel® 80219 General Purpose PCI Processor Identification Information Die Details Stepping Part Number QDF (Q)/ Specification Number (SL) Voltage (V) Intel® 80219 General Purpose PCI Processor Speed (MHz) A-0 FW80219M400 Q690 3.3 400 Samples A-0 FW80219M600 Q691 3.3 600 Samples A-0 FW80219M400 SL7CL 3.3 400 Production Material A-0 FW80219M600 SL7CM 3.
Intel® 80219 General Purpose PCI Processor Core Errata Core Errata 1. Boundary Scan Is Not Fully Compliant to the IEEE 1149.1 Specification Problem: The IEEE Standard 1149.1 specifies the boundary scan logic to support two main goals: 1.
Intel® 80219 General Purpose PCI Processor Core Errata 3. Undefined Data Processing-‘like’ Instructions are Interpreted as an MSR Instruction Problem: The instruction decode allows undefined opcodes, which look similar to the MSR (Move to Status register from an ARM register) instruction, to be interpreted as an MSR instruction. The mis-decoded MSR instruction also adds a SUBNV PC,0x4 to the instruction flow.
Intel® 80219 General Purpose PCI Processor Core Errata 6. Incorrect Decode of Unindexed Mode, Using Addressing Mode 5, Can Corrupt Protected Registers Problem: The instruction decoder incorrectly decodes the valid combination of P=0, U=1 and W=0, when using unindexed mode in addressing mode 5 (load and store coprocessor). In this case, the LDC or STC should produce consecutive address loads or stores, with no base update until the coprocessor signals that it has received enough data.
Intel® 80219 General Purpose PCI Processor Core Errata 10. Aborted Store that Hits the Data Cache May Mark Writeback Data As Dirty Problem: When there is an aborted store that hits clean data in the data cache (data in an aligned four word range, that has not been modified from the core, since it was last loaded in from memory or cleaned), the data in the array is not modified (the store is blocked), but the dirty bit is set.
Intel® 80219 General Purpose PCI Processor Core Errata 11. Performance Monitor Unit Event 0x1 Can Be Incremented Erroneously by Unrelated Events Problem: Event 0x1 in the performance monitor unit (PMU) can be used to count cycles in which the instruction cache cannot deliver an instruction. The only cycles counted should be those due to an instruction cache miss or an instruction TLB miss.
Intel® 80219 General Purpose PCI Processor Core Errata 13. Accesses to the CP15 ID register with opcode2 > 0b001 returns unpredictable values Problem: The ARM Architecture Reference Manual (ARM DDI 0100E) states the following in chapter B-2, section 2.3: “If an value corresponding to an unimplemented or reserved ID register is encountered, the System Control processor returns the value of the main ID register.
Intel® 80219 General Purpose PCI Processor Core Errata 15. Updating the JTAG parallel register requires an extra TCK rising edge Problem: IEEE 1149.1 states that the effects of updating all parallel JTAG registers should be seen on the falling edge of TCK in the Update-DR state. The Intel Xscale® core parallel JTAG registers incorrectly require an extra TCK rising edge to make the update visible.
Intel® 80219 General Purpose PCI Processor Non-Core Errata Non-Core Errata 1. The ATU Returns Invalid Data for the DWORD that Target Aborted from the MCU when Using 32-Bit Memory, ECC Enabled and in PCI Mode The external PCI bus requests a read through the ATU to the MCU, starting at the high DWORD. Remember the MCU is in 32-bit mode. The ATU requests multiple DWORDs since it pre-fetches, but starts at the high DWORD address. The MCU issues two DWORDs.
Intel® 80219 General Purpose PCI Processor Non-Core Errata 3. MCU Pointers are Incorrect following a Restoration from a Power Fail Problem: This issue occurs when: 1. There is a power failure (not during power management or normal shutdown). 2. When power is restored, the internal MCU pointers to the SDRAM may not be correct. 3.
Intel® 80219 General Purpose PCI Processor Non-Core Errata 6. The MTTR1 (Core Multi-Transaction Timer) is not operating due to improper behavior of the core internal bus request signal (REQ#) Problem: The MTTR1 (Core Multi-Transaction Timer) is not operating due to improper behavior of the core internal bus request signal (REQ#). All agents on the bus, except the core, maintain their assertion on REQ# signals upon receiving a retry.
Intel® 80219 General Purpose PCI Processor Non-Core Errata 8. Vih Minimum Input High Voltage (Vih) level for the PCI pins Problem: The Vih Minimum Input High Voltage (Vih) level for the PCI pins is being tested at 100 mV higher than the minimum Vih level specified in Table 4-3 (DC Specifications for 3.3 V Signaling) of the PCI Local Bus Specification, Revision 2.2. This Vih test limit only applies to cold temperature testing specified to be 0°C. The PCI Local Bus Specification, Revision 2.
Intel® 80219 General Purpose PCI Processor Specification Changes Specification Changes 1. Signal NC2 was renamed to P_BMI (AE23). New function added to signal P_BMI. The P_BMI (AE23) signal has been added to the Intel® 80219 general purpose PCI processor. This signal replaces, using an external GPIO pin for Initialization Device Select (IDSEL) control of an I/O device during host configuration cycles.
Intel® 80219 General Purpose PCI Processor Specification Changes Note: Figure 2. The host BIOS does not require any modifications to accommodate this implementation. All the responsibility for I/O device configuration and resource falls to the 80219 firmware.
Intel® 80219 General Purpose PCI Processor Specification Clarifications Specification Clarifications 1. The Intel® 80219 general purpose PCI processor is compliant with the PCI Local Bus Specification, Revision 2.2 but it is not compliant with PCI Local Bus Specification, Revision 2.3 Issue: The Intel® 80219 general purpose PCI processor was designed to be compliant with the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.
Intel® 80219 General Purpose PCI Processor Specification Clarifications 3. BAR0 Configuration When Using the Messaging Unit (MU) Issue: When the BAR0 is configured as a prefetchable register by default and a burst request crosses into or through the range of offsets 40h to 4Ch (i.e., this includes the Circular Queues), the transaction is signaled a Target Abort immediately on the PCI/PCI-X bus, which may be read as an NMI by the host BIOS. Status: Doc.
Intel® 80219 General Purpose PCI Processor Specification Clarifications 6. In-order Delivery not guaranteed for data blocks described by a single DMA descriptor Issue: In-order delivery is not guaranteed for data blocks described by a single DMA descriptor that crosses a 1 KB boundary. This may result in out of order execution of the DMA transfer. When multiple DMA descriptors are used the ordering is maintained with respect to the blocks described by each descriptor.
Intel® 80219 General Purpose PCI Processor Documentation Changes Documentation Changes None for this revision of this specification update.
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