Datasheet

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
APPENDIX
102
Table 54. Input Signals
Name Active Level Clock Signal Group Qualified
LINT[1:0] High Asynch CMOS Input APIC enabled mode
NMI High Asynch CMOS Input APIC disabled mode
PICCLK High — APIC Clock Always
PREQ# Low Asynch CMOS Input Always
PWRGD High Asynch CMOS Input Always
RESET# Low BCLK AGTL+ Input Always
RS[2:0]# Low BCLK AGTL+ Input Always
RSP# Low BCLK AGTL+ Input Always
SA[2:0] High SMBCLK Power/Other
SMBCLK# High — SMBus Clock Always
SLP# Low Asynch CMOS Input During Stop Grant state
SMI# Low Asynch CMOS Input
STPCLK# Low Asynch CMOS Input
TCK High — TAP Clock
TDI High TCK TAP Input
TMS High TCK TAP Input
TRST# Low Asynch TAP Input
TRDY# Low BCLK AGTL+ Input
WP High Asynch SMBus Input
OCVR_EN high Asynch Power/Other
Table 55. I/O Signals (Single Driver)
Name Active Level Clock Signal Group Qualified
A[35:03]# Low BCLK AGTL+ I/O ADS#, ADS#+1
ADS# Low BCLK AGTL+ I/O Always
AP[1:0]# Low BCLK AGTL+ I/O ADS#, ADS#+1
SELFSB0 High — Power/Other
SELFSB1 TBD TBD TBD TBD
BR0# Low BCLK AGTL+ I/O Always
BP[3:2]# Low BCLK AGTL+ I/O Always
BPM[1:0]# Low BCLK AGTL+ I/O Always
D[63:00]# Low BCLK AGTL+ I/O DRDY#
DBSY# Low BCLK AGTL+ I/O Always
DEP[7:0]# Low BCLK AGTL+ I/O DRDY#
DRDY# Low BCLK AGTL+ I/O Always
LOCK# Low BCLK AGTL+ I/O Always
REQ[4:0]# Low BCLK AGTL+ I/O ADS#, ADS#+1