Datasheet

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
ELECTRICAL SPECIFICATIONS
20
Table 8. CMOS, TAP, Clock and APIC Signal Groups, DC Specifications at the processor edge fingers
Symbol Parameter Min Max Unit Notes
V
IL
Input Low Voltage -0.150 0.7 V 6
V
IH
(PICCLK &
PWRGD only)
Input High Voltage 1.7
2.0
2.625
2.625
V
V
2.5V + 5% maximum, 7
2.5V + 5% maximum, 4, 5
V
OL
Output Low Voltage 0.5 V Parameter measured at 14mA
V
OH
Output High Voltage 2.625 V All outputs are open-drain to 2.5V
+ 5%
I
LI
Input Leakage Current ±100 µA 1
I
LO
Output Leakage
Current
±100 µA 2
Con I/O Pin Capacitance 25 pF 3
NOTES:
1. 0 ≤ V
IN
≤ 2.625V.
2. 0 ≤ V
OUT
≤ 2.625V.
3. Total capacitance of processor core and voltage clamp device. Does not include cartridge trace capacitance. Applies to all CMOS,
TAP, Clock, and APIC signals except BCLK, PICCLK and PWRGOOD.
4. This parameter applies to PICCLK.
5. This parameter applies to PWRDG.
6. Maximum V
IL
at the processor core pin is specified as 2/3 V
TT
– 0.2V.
7. Minimum V
IH
at the processor core pin is specified as 2/3 V
TT
+ 0.2V.