Datasheet

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
3
TABLE OF CONTENTS
PRODUCT FEATURES....................................................................................................................................................I
1. INTRODUCTION.....................................................................................................................................................6
2. TERMINOLOGY......................................................................................................................................................7
2.1 S.E.C. CARTRIDGE TERMINOLOGY........................................................................................................... 7
2.2 REFERENCES.................................................................................................................................................... 8
3. ELECTRICAL SPECIFICATIONS....................................................................................................................9
3.1 SYSTEM BUS AND VREF................................................................................................................................ 9
3.2 POWER AND GROUND PINS............................................................................................................................ 9
3.3 DECOUPLING GUIDELINES........................................................................................................................... 10
3.3.1 VCC_CORE ...................................................................................................................................................10
3.3.2 LEVEL 2 CACHE DECOUPLING...................................................................................................10
3.3.3 SYSTEM BUS AGTL+ DECOUPLING...........................................................................................10
3.4 CLOCK FREQUENCIES AND SYSTEM BUS CLOCK RATIOS...................................................................... 10
3.4.2 MIXING PROCESSORS OF DIFFERENT FREQUENCIES......................................................12
3.5 VOLTAGE IDENTIFICATION.......................................................................................................................... 12
3.6 SYSTEM BUS UNUSED PINS AND TEST PINS............................................................................................. 14
3.7 SYSTEM BUS SIGNAL GROUPS.................................................................................................................... 14
3.7.2 ASYNCHRONOUS VS. SYNCHRONOUS FOR SYSTEM BUS SIGNALS ................................15
3.8 ACCESS PORT (TAP) CONNECTION........................................................................................................... 15
3.9 MAXIMUM RATINGS..................................................................................................................................... 16
3.10 PROCESSOR DC SPECIFICATIONS............................................................................................................... 16
3.11 AGTL+ SYSTEM BUS SPECIFICATIONS..................................................................................................... 21
3.12 SYSTEM BUS AC SPECIFICATIONS............................................................................................................. 22
4. SIGNAL QUALITY................................................................................................................................................31
4.1 BUS CLOCK SIGNAL QUALITY SPECIFICATIONS.............................................................................................. 31
4.2 AGTL+ SIGNAL QUALITY SPECIFICATIONS............................................................................................. 31
4.2.1 AGTL+ Ringback Tolerance Specifications..........................................................................................32
4.2.2 AGTL+ OVERSHOOT/UNDERSHOOT GUIDELINES ..............................................................32
4.3 NON-GTL+ SIGNAL QUALITY SPECIFICATIONS.............................................................................................. 35
4.3.1 2.5V Signal Overshoot/Undershoot Guidelines .....................................................................................36
4.3.2 BCLK Overshoot/Undershoot Guidelines and Specifications.............................................................36
4.3.3 Measuring BCLK Overshoot/Undershoot................................................................................................37
4.3.4 2.5V TOLERANT BUFFER RINGBACK SPECIFICATION .................................................................37
4.3.5 2.5V TOLERANT BUFFER SETTLING LIMIT GUIDELINE .............................................................38
5. PROCESSOR FEATURES...................................................................................................................................39
5.1 LOW POWER STATES AND CLOCK CONTROL................................................................................................... 39
5.1.1 NORMAL STATE — STATE 1...........................................................................................................39
5.1.2 AUTO HALT POWER DOWN STATE — STATE 2 ......................................................................39
5.1.3 STOP-GRANT STATE — STATE 3 ..................................................................................................40
5.1.4 HALT/GRANT SNOOP STATE — STATE 4...................................................................................40
5.1.5 SLEEP STATE — STATE 5................................................................................................................41
5.1.6 CLOCK CONTROL.............................................................................................................................41
5.2 SYSTEM MANAGEMENT BUS (SMBUS) INTERFACE ................................................................................ 41
5.2.1 PROCESSOR INFORMATION ROM......................................................................................................42
5.2.2 SCRATCH EEPROM ..........................................................................................................................46
5.2.3 PROCESSOR INFORMATION ROM AND SCRATCH EEPROM SUPPORTED SMBUS
TRANSACTIONS.....................................................................................................................................................46
5.2.4 THERMAL SENSOR...........................................................................................................................47
5.2.5 THERMAL SENSOR SUPPORTED SMBUS TRANSACTIONS .................................................48
5.2.6 THERMAL SENSOR REGISTERS ...................................................................................................49
5.2.7 SMBus Device Addressing.................................................................................................................51
6. THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS..................................................53
6.1 THERMAL SPECIFICATIONS.......................................................................................................................... 53
6.1.1 POWER DISSIPATION ......................................................................................................................53
6.1.2 PLATE FLATNESS SPECIFICATION ............................................................................................55
6.2 PROCESSOR THERMAL ANALYSIS............................................................................................................... 55
6.2.1 THERMAL SOLUTION PERFORMANCE.....................................................................................55
6.2.2 THERMAL PLATE TO HEAT SINK INTERFACE MANAGEMENT GUIDE..........................56