Datasheet

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
ELECTRICAL SPECIFICATIONS
30
TCK
TDI, TMS
Input
Signals
TDO
Output
Signals
P6CB766a
1.25V
T
v
T
w
T
r
T
s
T
x
T
u
T
y
T
z
1.25V
T
r
T43 (All Non-Test Inputs Setup Time)=
T
s
T44 (All Non-Test Inputs Hold Time)=
T
u
T40 (TDO Float Delay)=
T
v
T37 (TDI, TMS Setup Time)=
T
w
T38 (TDI, TMS Hold Time)=
T
x
T39 (TDO Valid Delay)=
T
y
T41 (All Non-Test Outputs Valid Delay)=
T
z
T42 (All Non-Test Outputs Float Delay)=
Non-Test
Non-Test
Figure 9. Test Timings (Boundary Scan)
TRST#
P6CB-
1.25V
T
q
T
q
T36 (TRST# Pulse Width)=
Figure 10. Test Reset Timings