Datasheet

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
SIGNAL QUALITY
36
Undershoot
Overshoot
Settling Limit
Settling Limit
Rising-Edge
Ringback
Falling-Edge Ringback
V
LO
V
SS Time
V =
HI
V
CC
2.5
Voltage
RINGBACK
Figure 14. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback
4.3.1 2.5V Signal Overshoot/Undershoot Guidelines
The Overshoot/Undershoot guideline limits transitions beyond V
CC
or V
SS
due to fast signal edge rates. Refer to Figure
14 for an illustration of Overshoot/Undershoot specifications for non-AGTL+ signals. The processor may be damaged if
Overshoot/Undershoot specifications are not met. The Overshoot/Undershoot specification is shown in Table 23.
Table 23. 2.5V Tolerant Signal Group Overshoot/Undershoot at the Processor Core Pins
1,2,3,4,5,6,7,8,9
Overshoot/Undershoot Max Pulse Duration (nS)
Magnitude AF = 0.01 AF = 0.1 AF = 1
2.3 60 16.8 1.6
2.25 60 30.4 3
2.2 60 56 5.6
2.15 60 60 8
2.1 60 60 19.2
2.05 60 60 60
2.0 60 60 60
NOTES:
1. Activity Factor based on period equal to 30 nS.
2. Overshoot/Undershoot Magnitude = 2.3V is an Absolute value and should never be exceeded.
3. Overshoot is measured relative to VSS.
4. Undershoot is measured relative to VTT.
5. Overshoot/Undershoot Pulse Duration is measured relative to 1.635V.
6. Rinback below VTT cannot be subtracted from Overshoots/Undershoots.
7. Lesser Undershoot does not allocate longer or larger Overshoot.
8. OEM's are encouraged to follow Intel provided layout guidelines.
9. All values specified by design characterization.
4.3.2 BCLK Overshoot/Undershoot Guidelines and Specifications
Unlike AGTL+ or CMOS signals, BCLK Specifications do not provide for any relaxation due to activity factor. System
designers should ensure that their platforms meet the BCLK specifications even under worst-case conditions.