Datasheet

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
PROCESSOR FEATURES
44
Table 26. processor Information ROM Format
Offset/Section # of Bits Function Notes
HEADER: 00h 8 Data Format Revision Two 4-bit hex digits
01h 16 EEPROM Size Size in bytes (MSB first)
03h 8 processor Data Address Byte pointer, 00h if not present
04h 8 processor Core Data Address Byte pointer, 00h if not present
05h 8 L2 Cache Data Address Byte pointer, 00h if not present
06h 8 SEC Cartridge Data Address Byte pointer, 00h if not present
07h 8 Part Number Data Address Byte pointer, 00h if not present
08h 8 Thermal Reference Data
Address
Byte pointer, 00h if not present
09h 8 Feature Data Address Byte pointer, 00h if not present
0Ah 8 Other Data Address Byte pointer, 00h if not present
0Bh 16 Reserved Reserved for future use
0Dh 8 Checksum 1 byte checksum
PROCESSOR: 0Eh 48 S-spec/QDF Number Six 8-bit ASCII characters
2 Sample/Production 00b = Sample only
6 Reserved Reserved for future use
8 Checksum 1 byte checksum
CORE: 16h 2 processor Core Type From CPUID
4 processor Core Family From CPUID
(Family 6)
4 processor Core Model From CPUID
(Model 8)
4 processor Core Stepping From CPUID
2 Reserved
16 OCVR option 2
Input Voltage ID
Voltage in mV
(0=2.8V, 12000=5/12V
16 OCVR option 2
Input Voltage Tolerance
Edge finger tolerance in mV, +/-
(0=2.8V, 600=5/12V)
8 Reserved Reserved for future use
16 Maximum Core Frequency 16-bit binary number (in MHz)
16 OCVR option 1
Input Voltage ID
Voltage in mV
(2800=2.8V, 5000=5/12V)
16 OCVR option 1
Input Voltage Tolerance
Edge finger tolerance in mV, +/-
(85=2.8V, 250=5/12V)
8 Reserved Reserved for future use
8 Checksum 1 byte checksum
L2 CACHE: 25h 32 Reserved Reserved