Datasheet
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
MECHANICAL SPECIFICATIONS
64
7.3 Substrate Edge Finger Signal Listing
Table 44 is the Pentium® III Xeon™ processor at 600 MHz+ substrate edge finger listing in order by pin
number. Table 45 is the Pentium III Xeon processor at 600 MHz+ substrate edge connector listing in order by
pin name. These tables reflect the new SC330.1 pin definition, new or changed pins definitions are shown in
bold.
Table 44. Signal Listing in Order by Pin Number
Pin
No. Pin Name Signal Buffer Type
Pin
No. Pin Name Signal Buffer Type
A1 RESERVED_A1 DO NOT
CONNECT
B1 PWR_EN[1] Short to PWR_EN[0]
A2 VCC_TAP TAP Supply B2 VCC_CORE Cartridge VCC
A3 HV_EN# OPEN (2.8V
Pentium III Xeon
processor)
SHORT (5/12V
Pentium III Xeon
processor)
B3 OCVR_OK Open Drain Output
A4 VSS Ground B4 TEST_VSS_B4 Pull down to V
SS
A5 VTT AGTL+ V
TT
Supply B5 VCC_CORE Cartridge VCC
A6 VTT
AGTL+ V
TT
Supply
B6 VTT AGTL+ V
TT
Supply
A7 SELFSB1 CMOS Output B7 VTT AGTL+ V
TT
Supply
A8 VSS Ground B8 VCC_CORE Cartridge VCC
A9 SELFSB0 CMOS Input B9 RESERVED_B9 DO NOT CONNECT
A10 VSS Ground B10 FLUSH# CMOS Input
A11 RESERVED_A11 DO NOT
CONNECT
B11 VCC_CORE Cartridge VCC
A12 IERR# CMOS Output B12 SMI# CMOS Input
A13 VSS Ground B13 INIT# CMOS Input
A14 A20M# CMOS Input B14 VCC_CORE Cartridge VCC
A15 FERR# CMOS Output B15 STPCLK# CMOS Input
A16 VSS Ground B16 TCK TAP Clock
A17 IGNNE# CMOS Input B17 VCC_CORE Cartridge VCC
A18 TDI TAP Input B18 SLP# CMOS Input
A19 VSS Ground B19 TMS TAP Input
A20 TDO TAP Output B20 VCC_CORE Cartridge VCC
A21 PWRGD CMOS Input B21 TRST# TAP Input
A22 VSS Ground B22 RESERVED_B22 DO NOT CONNECT
A23 TEST_2.5_A23 Pull up to 2.5V B23 VCC_CORE Cartridge VCC
A24 THERMTRIP# CMOS Output B24 RESERVED_B24 DO NOT CONNECT
A25 VSS Ground B25 RESERVED_B25 DO NOT CONNECT
A26 OCVR_EN CMOS INPUT B26 VCC_CORE Cartridge VCC
A27 LINT[0] CMOS Input B27 TEST_2.5_B27 Pull up to 2.5V
A28 VSS Ground B28 LINT[1] CMOS Input
A29 PICD[0] CMOS I/O B29 VCC_CORE Cartridge VCC
A30 PREQ# CMOS Input B30 PICCLK APIC Clock Input
A31 VSS Ground B31 PICD[1] CMOS I/O
A32 BP#[3] AGTL+ I/O B32 VCC_CORE Cartridge VCC
A33 BPM#[0] AGTL+ I/O B33 BP#[2] AGTL+ I/O
A34 VSS Ground B34 RESERVED_B34 DO NOT CONNECT
A35 BINIT# AGTL+ I/O B35 VCC_CORE Cartridge VCC
A36 DEP#[0] AGTL+ I/O B36 PRDY# AGTL+ Output
A37 VSS Ground B37 BPM#[1] AGTL+ I/O
A38 DEP#[1] AGTL+ I/O B38 VCC_CORE Cartridge VCC