Datasheet

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PENTIUM® III XEON™ PROCESSOR AT 700 MHz

and 900 MHz.

Datasheet

Product Features

 Binary compatible with applications

running on previous members of

the Intel microprocessor family

 Optimized for 32-bit applications

running on advanced 32-bit

operating systems

 Dynamic Independent Bus

architecture: separate dedicated

external 100 MHz System Bus and

dedicated internal cache bus

operating at full processor core

speed

 Power Management capabilities

 System Management mode

 Multiple low-power states

 Single Edge Contact (S.E.C.)

cartridge packaging technology; the

S.E.C. cartridge delivers high

performance processing and bus

technology to mid range to high end

servers and workstations

 100 MHz system bus speeds data

transfer between the processor and

the system

 Integrated high performance16k

instruction and 16k data, non-

blocking, level-one cache

 Available in 1MB (700 MHz) or 2MB

(900 MHz and 700 MHz) unified,

non-blocking level-two cache

 Enables systems which are

scaleable up to two processors and

64GB of physical memory

 SMBus interface to advanced

manageability features

 Streaming SIMD Extensions for

enhanced video, sound and 3D

performance

The Intel® Pentium® III Xeon™ Processor at 700 MHz with 1MB or 2MB L2 cache and 900 MHz with 2MB L2

cache is designed for mid-range to high-end servers and workstations, and is binary compatible with previous

Intel® Architecture processors. The Pentium® III Xeon™ processor at 700 MHz and 900 MHz provides the

best performance available for applications running on advanced operating systems such as Microsoft*

Windows* 98, Microsoft* Windows* NT*, and UNIX*. The processor is scalable to four processors in a

multiprocessor system and extends the power of the Pentium® Pro processor with new features designed to

make this processor the right choice for powerful workstation, advanced server management, and mission-

critical applications. Pentium® III Xeon™ processor at 700 MHz and 900 MHz-based workstations offer the

memory architecture required by the most demanding workstation applications and workloads. Specific

features of the processor address platform manageability to meet the needs of a robust IT environment,

maximize system up time and ensure optimal configuration and operation of servers. The Pentium® III

Xeon™ processor at 700 MHz and 900 MHz enhances the ability of server platforms to monitor, protect, and

service the processor and its environment.

Order Number: 248711-002

March 2001

Summary of content (105 pages)

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PENTIUM® III XEON™ PROCESSOR AT 700 MHz and 900 MHz.
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Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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TABLE OF CONTENTS TABLE OF CONTENTS PRODUCT FEATURES ............................................................................................................ I 1. INTRODUCTION ......................................................................................................................... 6 2. TERMINOLOGY .......................................................................................................................... 7 2.1 S.E.C. CARTRIDGE TERMINOLOGY..................................
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TABLE OF CONTENTS 5.1.3 STOP-GRANT STATE — STATE 3......................................................................... 42 5.1.4 HALT/GRANT SNOOP STATE — STATE 4 ........................................................... 42 5.1.5 SLEEP STATE — STATE 5..................................................................................... 43 5.1.6 CLOCK CONTROL .................................................................................................. 43 5.2 SYSTEM MANAGEMENT BUS (SMBUS) INTERFACE .
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TABLE OF CONTENTS 10.1 ALPHABETICAL SIGNALS REFERENCE ..................................................................................... 90 10.1.1 A[35:03]# (I/O)............................................................................................................... 90 10.1.2 A20M# (I) ...................................................................................................................... 90 10.1.3 ADS# (I/O)............................................................................
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TABLE OF CONTENTS 10.1.55 TDI (I) ........................................................................................................................ 101 10.1.56 TDO (O) .................................................................................................................... 101 10.1.57 TEST_2.5_[A23, A62, B27] (I) .................................................................................. 101 10.1.58 THERMTRIP# (O) .....................................................................
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INTRODUCTION 1. INTRODUCTION The Pentium® III Xeon™ processor at 700 MHz and 900 MHz, like the Pentium® Pro, Pentium® II, Pentium® II Xeon™ and previous Pentium® III Xeon™ processors, implements a Dynamic Execution micro-architecture, a unique combination of multiple branch prediction, data flow analysis, and speculative execution.
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TERMINOLOGY 2. TERMINOLOGY In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a signal is in the active state (based on the name of the signal) when driven to a low level. For example, when FLUSH# is low, a flush has been requested. When NMI is high, a non-maskable interrupt has occurred.
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TERMINOLOGY Additional terms referred to in this and other related documentation: • SC330.1 — An enhanced electrical and mechanical interface based on the SC330 (formerly Slot2) interface that defines additional signals and electrical requirements to support an OCVR (On Cartridge Voltage Regulator), a processor core and a System Bus frequency of 100 MHz for 4-way designs. Refer to Chapter 10 for details. • Retention mechanism — A mechanical component designed to hold the processor in a SC330 connector.
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ELECTRICAL SPECIFICATIONS 3. ELECTRICAL SPECIFICATIONS 3.1 System Bus and VREF The Pentium® III Xeon™ processor signals use a variation of the Pentium® Pro processor GTL+ signaling technology. The Pentium® III Xeon™ processor differs from the Pentium® II processor and Pentium® Pro processor in its output buffer implementation.
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ELECTRICAL SPECIFICATIONS For a summary of the power and ground pins listed above, see Table 50 and Table 51 in section 7.3 of this document for signal listings by Pin Number and Pin Name.
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ELECTRICAL SPECIFICATIONS 3.3 Decoupling Guidelines Due to the large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This causes voltages on power planes to sag below their nominal values if bulk decoupling is not adequate. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 5.
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ELECTRICAL SPECIFICATIONS Table 1 System Bus-to-Core Frequency Ratio Configuration1 Ratio of BCLK to Core Frequency 1/4 (Safe-LLLL) 1/7 2/182 1/4(Safe-HHHH) 100 MHz Target Frequency 700 MHz 900 MHz EBL PWRUP Reg[27, 25:22] 0 0011 0 1001 1 0000 0 1100 LINT[1] L H X H LINT[0] L L X H IGNNE# L H X H A20M# L L X H NOTES: 1. The frequency multipliers supported are shown in Table 1; other combinations will not be validated nor supported by Intel. Also, each 2.
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ELECTRICAL SPECIFICATIONS 2.5 V 2.5 V 1K Ω Mux A20M# 1-4 Processors IGNNE# LINT1/NMI LINT0/INTR Set Ratio: CRESET#2 000809 Figure 2. Logical1 Schematic for Clock Ratio Pin Sharing NOTES: 1. Signal Integrity issues may require this circuit to be modified 2. Current Intel® 840 chipsets do not implement the CRESET# signal. 3.4.2 MIXING PROCESSORS OF DIFFERENT FREQUENCIES Mixing components of different internal clock frequencies is not supported and has not been validated by Intel.
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ELECTRICAL SPECIFICATIONS VID_CORE[4:0] controls the voltage supply to the processor core and VID_L2[4:0] controls the voltage supply to the L2 cache (in the case of the Pentium® II Xeon™ processor and Pentium® III Xeon™ processor at 500 MHz and 550 MHz). Both core and L2 use the same encoding as shown in Table 2. They are not driven signals, but are either an open circuit or a short circuit to VSS.
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ELECTRICAL SPECIFICATIONS Table 2. FMB Core and L2 Voltage Identification Definition 1, 2 Processor pins VID4 VID3 VID2 VID1 VID0 00110b – 01111b Vcc Core3 L23,5 Reserved 2 0 0 1 0 1 1.80 X X 0 0 1 0 0 1.85 X X 0 0 0 1 1 1.90 X X 0 0 0 1 0 1.95 X X 0 0 0 0 1 2.00 X X 0 0 0 0 0 2.05 X X 1 1 1 1 0 2.1 X 1 1 1 0 1 2.2 X 1 1 1 0 0 2.3 X 1 1 0 1 1 2.4 X 1 1 0 1 0 2.5 X 1 1 0 0 1 2.
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ELECTRICAL SPECIFICATIONS pull-ups. A resistor of greater than or equal to 10KΩ may be used to connect the VID signals to the converter input. See the VRM 8.3 DC–DC Converter Design Guidelines for further information. 3.6 System Bus Unused Pins and Test Pins Unless otherwise specified, All RESERVED_XXX pins must remain unconnected. Note that pins that are newly marked as RESERVED in this document may be tied to a power rail in existing baseboards.
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ELECTRICAL SPECIFICATIONS Table 3.
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ELECTRICAL SPECIFICATIONS A Debug Port is described in Chapter 8. The Debug Port must be placed at the start and end of the TAP chain with TDI to the first component coming from the Debug Port and TDO from the last component going to the Debug Port. In an MP system, be cautious when including an empty SC330 connector in the scan chain.
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ELECTRICAL SPECIFICATIONS NOTE Unless otherwise noted, each specification applies to all Pentium® III Xeon™ processor at 700 MHz and 900 MHz. Where differences exist between processors, look for the table entries identified by “FMB” in order to design a Flexible Mother Board (FMB) capable of accepting the Pentium® III Xeon™ processor at 700 MHz and 900 MHz as well as the Pentium® II Xeon™ processor and previous versions of the Pentium® III Xeon™ processor.
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ELECTRICAL SPECIFICATIONS Table 6. Current Specifications 1,10 Symbol Parameter Icc_core Min Typ Max Unit Notes 700 MHz 13.9 A 2 @ 2.74V VCC_CORE 900 MHz 17.0 Icc_core 700 MHz 8.4 A 2 @ 4.75V VCC_CORE 900 MHz 10.3 A 2 A 1, 2, 10 Icc_core 700 MHz 3.5 @ 11.4V VCC_CORE 900 MHz 4.3 Icc_core FMB 2.74V 19.0 4.75V 11.0 11.4V 5.0 IVTT Termination voltage supply current ISGnt ICC Stop Grant for processor core 0 0.3 1.2 A 4 - - 10.0 A 3,5 A 3 2.8V 5.6 5.
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ELECTRICAL SPECIFICATIONS 8. 9. 10. VCC_SMB must be connected to 3.3V power supply (even if the SMBus features are not used) in order for the processor to function properly. A disabled processor OCVR draws approximately 46 mA at 2.8V VCC_CORE from the motherboard VRM. If your system needs to maintain VRM regulation with a disabled processor (OCVR_EN inactive), the VRM output minimum load specification should be 46 mA or less. The FMB specification is applicable to 2.
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ELECTRICAL SPECIFICATIONS 6. 7. Maximum VIL at the processor core pin is specified as 2/3 VTT – 0.2V. Minimum VIH at the processor core pin is specified as 2/3 VTT + 0.2V. Table 9. SMBus Signal Group, DC Specifications at the processor edge fingers Symbol Parameter Min Max Unit VIL Input Low Voltage -0.3 0.3 x VccSMB V VIH Input High Voltage 0.7 x VccSMB 3.465 V VOL Output Low Voltage 0.
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ELECTRICAL SPECIFICATIONS Table 11 Internal Parameters for the AGTL+ Bus Symbol Parameter RTT Termination Resistor VREF Bus Reference Voltage Min Typ Max 150 0.733 VTT 100mV 0.733 VTT 0.733 VTT + 100mV Units Notes Ohm 1 V 2 NOTES: 1. 2. The Pentium® III Xeon™ processor at 700 MHz and 900 MHz contains on-die termination resistors with +/-10% tolerance. VREF is generated on the processor substrate.
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ELECTRICAL SPECIFICATIONS 3.12 System Bus AC Specifications The system bus timings specified in this section are defined at the processor core pins unless otherwise noted. Timings are tested at the processor core during manufacturing. NOTE: Timing specifications T45-T49 are reserved for future use. All system bus AC specifications for the AGTL+ signal group are relative to the rising edge of the BCLK input.
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ELECTRICAL SPECIFICATIONS Table 12. System Bus AC Specifications (Clock) at the processor Core Pins 1, 2, 3 T# Parameter System Bus Frequency Min Nom Max Unit 90 100.2 MHz 10.0 11.11 nS ±150 pS Figure Notes 4 T1: BCLK Period 4 4, 5, 9 T2: BCLK Period Stability T3: BCLK High Time 2.5 nS 4, 12 @>2.0V, 9 T4: BCLK Low Time 2.5 nS 4, 12 @<0.5V, 9 T5: BCLK Rise Time 0.50 1.5 nS 4, 12 0.5V–2.0V 8, 9 T6: BCLK Fall Time 0.50 1.5 nS 4, 12 2.0V–0.
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ELECTRICAL SPECIFICATIONS Table 14. AGTL+ Signal Group, System Bus AC Specifications at the Core Pins1 RL = 25 ohms Terminated to 1.5V T# Parameter Min Max Unit Figure Notes T7: AGTL+ Output Valid Delay -0.07 2.65 nS Figure 5 2, 8 T8: AGTL+ Input Setup Time 1.20 nS Figure 6 3, 4, 6, 8 T9: AGTL+ Input Hold Time 0.62 nS Figure 6 5 T10: RESET# Pulse Width 1.00 mS Figure 8 5 NOTES: 1. 2. 3. 4. 5. 6. 7. 8. These specifications are tested during manufacturing.
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ELECTRICAL SPECIFICATIONS Table 16.
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ELECTRICAL SPECIFICATIONS Table 18. System Bus AC Specifications (TAP Connection) at the processor Core 1 T# Parameter Min T30: TCK Frequency T31: TCK Period 60.0 nS Figure 3 T32: TCK High Time 25.0 nS Figure 3 @1.7V 2 T33: TCK Low Time 25.0 nS Figure 3 @0.7V 2 T34: TCK Rise Time 5.0 nS Figure 3 (0.7V–1.7V) 2, 3 T35: TCK Fall Time 5.0 nS Figure 3 (1.7V–0.7V) 2, 3 T36: TRST# Pulse Width 40.0 nS Figure 10 (Asynchronous) 2 T37: TDI, TMS Setup Time 5.
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ELECTRICAL SPECIFICATIONS Table 19. SMBus Signal Group, AC Specifications at the Edge Fingers T# Parameter Min Max Unit 100 KHz T50: SMBCLK Frequency T51: SMBCLK Period 10 uS Figure 4 T52: SMBCLK High Time 4.0 uS Figure 4 T53: SMBCLK Low Time 4.7 uS Figure 4 T54: SMBCLK Rise Time 1.0 uS Figure 4 T55: SMBCLK Fall Time 0.
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ELECTRICAL SPECIFICATIONS Th Tr 2.97V 2.46V 0.84V SCLK 0.84V Tf Tl Tr = T54 Tf = T55 Th = T52 Tl = T53 SMBUSCLK Figure 4. SMBCLK Clock Waveform Clock Tx Tx Signal V Valid Valid Tpw Tx = T7, T29 (Valid Delay) Tpw = T14, T15 (Pulse Wdith) V = 2/3 V TT for GTL+ signal group; 1V for CMOS, and APIC signal groups Figure 5.
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ELECTRICAL SPECIFICATIONS BCLK Tu Tt RESET# Tv Configuration (A20M#, IGNNE#, LINT[1:0]) Ty Tz Tx Safe Valid Tw Configuration (A[14:5]#, BR0#, FLUSH#, INIT#) Valid Tt = T9 (GTL+ Input Hold Time) Tu = T8 (GTL+ Input Setup Time) Tv = T10 (RESET# Pulse Width) Tw = T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time) Tx = T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time) T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time) Ty = T19 (Re
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ELECTRICAL SPECIFICATIONS 1.25V TCK Tv Tw Tr Ts 1.25V TDI, TMS Non-Test Input Signals Tx Tu Ty Tz TDO Non-Test Output Signals Tr = T43 (All Non-Test Inputs Setup Time) Ts = T44 (All Non-Test Inputs Hold Time) Tu = T40 (TDO Float Delay) Tv = T37 (TDI, TMS Setup Time) Tw = T38 (TDI, TMS Hold Time) Tx = T39 (TDO Valid Delay) Ty = T41 (All Non-Test Outputs Valid Delay) Tz = T42 (All Non-Test Outputs Float Delay) 6C Figure 9. Test Timings (Boundary Scan) TRST# 1.
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SIGNAL QUALITY 4. Signal Quality Signals driven on the system bus should meet signal quality specifications to ensure that the components read data properly and to ensure that incoming signals do not affect the long-term reliability of the component. Specifications are provided for simulation at the processor core. Meeting the specifications at the processor core in Table 21 through Table 27 ensures that signal quality effects will not adversely affect processor operation. 4.
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SIGNAL QUALITY 4.2 AGTL+ Signal Quality Specifications Refer to the Pentium II Processor Developer's Manual (Order Number 243341) for the specification for AGTL+. 4.2.2 AGTL+ Signal Quality Specifications Figure 12A illustrates the AGTL+ signal quality specifications for the processor for use in verifying signal quality at the processor core pins. These receiver signal quality specifications do not include overdrive region, ringback threshold, edge rate, and nonmonotonicity values.
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SIGNAL QUALITY Overshoot/Undershoot is the absolute value of the maximum voltage differential across the input buffer relative to the termination voltage (VTT). The overshoot/undershoot guideline limits transitions beyond VTT or VSS due to the fast signal edge rates. The processor can be damaged by repeated Overshoot/Undershoot events on 1.5 V or 2.5 V tolerant buffers if the potential is large enough (i.e., if the overshoot/undershoot is great enough).
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SIGNAL QUALITY The overshoot/undershoot specifications listed in the following tables specify the allowable overshoot/undershoot for a single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events that will each have their own set of parameters (duration, AF and magnitude). While each overshoot on its own may meet the overshoot specification, when you add the total impact of all overshoot events, the system may fail.
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SIGNAL QUALITY 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Unless otherwise noted, all guidelines in this table apply to all processor frequencies. Overshoot Magnitude and Undershoot Magnitude are absolute values and should never exceed 2.3V under any circumstances. Overshoot is measured relative to VSS. Undershoot is measured relative to VTT. Overshoot/Undershoot Pulse Duration is measured relative to 1.635V. Ringback below VTT cannot be subtracted from Overshoots/Undershoots.
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SIGNAL QUALITY pads. Overshoot/Undershoot shown in Figure 14 is for illustrative purposes only to help explain Ringback and Settling Limit. Refer to Figure 13 for an illustration of Overshoot/Undershoot specifications. O vershoot S ettling Lim it V =H I V CC 2 .5 R ising-E dge R ingback F alling-E dge R ingback V o ltag e S ettling Lim it V LO V SS T im e U ndershoot RINGBACK Figure 14. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback 4.3.1 2.
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SIGNAL QUALITY 1. 2. 3. 4. 5. 6. 7. 8. 9. Activity Factor based on period equal to 30 nS. Overshoot/Undershoot Magnitude = 2.3V is an Absolute value and should never be exceeded. Overshoot is measured relative to VSS. Undershoot is measured relative to VTT. Overshoot/Undershoot Pulse Duration is measured relative to 1.635V. Ringback below VTT cannot be subtracted from Overshoots/Undershoots. Lesser Undershoot does not allocate longer or larger Overshoot.
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SIGNAL QUALITY 4.3.4 2.5V TOLERANT BUFFER RINGBACK SPECIFICATION The ringback specification is the voltage at a receiving pin that a signal rings back to after achieving its maximum absolute value. (See Figure 14 for an for an illustration of ringback.) Excessive ringback can cause false signal detection or extend the propagation delay. Violations of the signal ringback specification are not allowed for 2.5V tolerant signals. Table 30 shows signal ringback specifications for the 2.
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PROCESSOR FEATURES 5. PROCESSOR FEATURES 5.1 Low Power States and Clock Control The processor allows the use of Auto HALT, Stop-Grant, and Sleep states to reduce power consumption by stopping the clock to specific internal sections of the processor, depending on each particular state. There is no Deep Sleep state on the processor. Refer to the following sections on low power states for the processor.
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PROCESSOR FEATURES HA L T Instruction and HA L T Bus Cycle Generated 2. Auto H AL T Power Down State BCL K running. Snoops and interrupts allowed. INIT#, BINIT#, INTR, NM I, SM I#, RESET# ST P C Snoop Event Occurs Snoop Event Serviced 4. H AL T /Grant Snoop State BCL K running. Service snoops to caches. ST P C LK# LK# 1. Nor mal State Normal execution. A sse rted STPCL K # A sserted D e-a ssert ed Snoop Event Occurs Snoop Event Serviced STPCL K # De-asserted 3.
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PROCESSOR FEATURES 5.1.5 SLEEP STATE — STATE 5 The Sleep state is a very low power state in which the processor maintains its context, maintains the PLL, and has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the StopGrant state (verified by the termination of the Stop-Grant Bus transaction cycle), the SLP# pin can be asserted, causing the processor to enter the Sleep state.
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PROCESSOR FEATURES R 10K 1/16W 5% OEM EEPROM INTEL CPU EEPROM Vcc Vcc R 10K 1/16W 5% A0 WP A0 WP A1 SC A1 SC A2 SD A2 SD R 10K 1/16W 5% A2D R 10K 1/16W 5% A Core C Stby ALERT Vcc# A0 SC A1 SD R 10K 1/16W 5% R 10K 1/16W 5% R 10K 1/16W 5% R 10K 1/16W 5% SA1 R 10K 1/16W 5% SDA SCL WP R 10K 1/16W 5% SA0 SMB_V SA2 SMBALERT 1 Figure 16. Logical Schematic of SMBus Circuitry NOTES: 1. 5.2.1 Actual implementation may vary.
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PROCESSOR FEATURES Systems implementing analog sensing should read the PIROM first, then compare that value with the measured VIN_SENSE rather than assuming any specific value. The value of AN_CORE_VSENSE is implementation dependent and cannot be assumed to be any particular value. Systems may derive benefit by monitoring its stability, but should not make assumptions about its value. In Table 31, text in bold represents the new defined fields for the Pentium® III Xeon™ processor at 700 MHz and 900 MHz.
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PROCESSOR FEATURES Table 31.
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PROCESSOR FEATURES CARTRIDGE: 32h PART NUMBERS: 38h THERMAL REF.: 70h FEATURES: 74h OTHER: 7Eh 16 L2 Cache Size 16-Bit binary number (in Kbytes) 8 Reserved 16 OCVR Output Voltage ID1 Voltage in mV 8 OCVR Output Voltage Tolerance, High Core tolerance in mV, + 8 OCVR Output Voltage Tolerance, Low Core tolerance in mV, - 8 Reserved Reserved for future use 8 Checksum 1 byte checksum 32 Cartridge Revision Four 8-bit ASCII characters 2 Substrate Rev.
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PROCESSOR FEATURES 5.2.2 SCRATCH EEPROM Also available on the SMBus is an EEPROM that may be used for other data at the system or processor vendor’s discretion. This device has a pull-down on the WP control pin through a 10KΩ resistor, as implemented on all previous Pentium® II Xeon™ and Pentium® III Xeon™ processors. This will allow the OEM EEPROM to be programmed in systems with no manipulation of this signal.
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PROCESSOR FEATURES Table 33. Receive Byte SMBus Packet S Device Address R/ W* A* Data A* P 1 7 bits 1 0 8 bits 1 1 Table 33 diagrams the Receive Byte packet that performs as a current address read. A device select address field and a read flag follow the start condition. The device decodes its address and drives acknowledge low. The data is returned by the device and the transfer is terminated by the controller providing negative acknowledge and a stop.
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PROCESSOR FEATURES uniquely determined for each unit. The procedure causes each unit to dissipate its maximum power (which can vary from unit to unit) while at the same time maintaining the thermal plate at its maximum specified operating temperature. Correctly used, this feature permits an efficient thermal solution while preserving data integrity. The thermal byte reading can be used in conjunction with the Thermal Reference Byte in the processor Information ROM.
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PROCESSOR FEATURES 1. This is an 8-bit field. The device that sent the alert will respond to the ARA Packet with its address in the seven most significant bits. The least significant bit is undefined and may return as a ‘1’ or ‘0’. See Section 5.2.7 for details on the Thermal Sensor Device addressing. Table 41.
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PROCESSOR FEATURES 5.2.6.3 Status Register The status register shown in Table 42 indicates which (if any) thermal value thresholds have been exceeded. It also indicates if a conversion is in progress or if an open circuit has been detected in the processor core thermal diode connection. Once set, alarm bits stay set until a status register read clears them. A successful read to the status register will clear any alarm bits that may have been set, unless the alarm condition persists. Table 42.
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PROCESSOR FEATURES 5.2.7 03h 0.5 04h 1 05h 2 06h 4 07h 8 08h to FFh Reserved for future use SMBus Device Addressing Of the addresses broadcast across the SMBus, the memory components claim those of the form “1010XXYZb”. The “XX” and “Y” bits are used to enable the devices on the cartridge at adjacent addresses. The Y bit is hard-wired on the cartridge to VSS (‘0’) for the Scratch EEPROM and pulled to VCC_SMB (‘1’) for the processor Information ROM.
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PROCESSOR FEATURES Table 45. Thermal Sensor SMBus Addressing Address (Hex) Upper Address1 8-bit Address Word on Serial Bus Slot Select 3Xh 5Xh SA1 SA2 b[7:0] 0011 0 0 0011000Xb 0011 1 0 0011010Xb 0 Z2 0101001Xb 0101 1 Z2 0101011Xb 1001 0 1 1001100Xb 1001 1 1 1001110Xb 0101 9Xh NOTES: 1. 2. Upper address bits are decoded in conjunction with the select pins. A tri-state or “Z” state on this pin is achieved by leaving this pin unconnected.
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THERMAL SPECIFICATIONS 6. THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS The processor contains a thermal plate for heatsink attachment. The thermal plate interface is intended to provide for multiple types of thermal solutions. This chapter will provide the necessary data for a thermal solution to be developed. See Figure 17 for thermal plate location. Figure 17. Thermal Plate View 6.1 Thermal Specifications This section provides power dissipation specifications for each version of the processor.
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THERMAL SPECIFICATIONS Table 47 Power Estimates 1 Core Power2 (W) 2.8V OCVR Power (W) 5V/12V OCVR Power (W) 2.8V Cartridge Power 3 (W) 5V/12V Cartridge Power 3 (W) 2.8V Thermal Power 4,8 (W) 5V/12V Thermal Power 4,8 (W) Power5 Min Tplate °C Max Tplate °C 700/100 25.9 6.1 7.3 32.0 33.2 28.9 29.6 2 0 65 900/100 31.8 7.5 9.0 39.3 40.8 35.5 36.3 2 0 65 50 50 0 65 Frequency FMB6 AGTL+ NOTES: 1. 2. 3. 4. 5. 6. 7. 8.
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THERMAL SPECIFICATIONS 6.1.2 PLATE FLATNESS SPECIFICATION The thermal plate flatness for the processor is specified to 0.010” across the entire thermal plate surface, with no more than a 0.003” step anywhere on the surface of the plate, as shown in Figure 18. Figure 18. Plate Flatness Reference 6.2 Processor Thermal Analysis 6.2.1 THERMAL SOLUTION PERFORMANCE Processor cooling solutions should attach to the thermal plate. The processor cover is not designed for thermal solution attachment.
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THERMAL SPECIFICATIONS the design of the heatsink and airflow around the heatsink. General Information on thermal interfaces and heatsink design constraints can be found in AP-586, Pentium II Processor Thermal Design Guidelines (Order Number 243331). 6.2.2 THERMAL PLATE TO HEAT SINK INTERFACE MANAGEMENT GUIDE Figure 19 shows suggested interface agent dispensing areas when using either Intel suggested interface agent.
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THERMAL SPECIFICATIONS To ensure functional and reliable processor operation, the processor's thermal plate temperature (TPLATE) must be maintained at or below the maximum TPLATE and at or above the minimum TPLATE specified in Table 47 and 48. Power from the processor core is transferred to the thermal plate at 2 locations. Figure 20 and 21 shows the locations for TPLATE measurement directly above these transfer locations.
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MECHANICAL SPECIFICATIONS 7. MECHANICAL SPECIFICATIONS The processor use S.E.C. cartridge package technology. The S.E.C. cartridge contains the processor core, OCVR and other components. The S.E.C. cartridge package connects to the baseboard through an edge connector. Mechanical specifications for the processor are given in this section. See Section 1.1.1 for a complete terminology listing. Figure 22 shows the thermal plate side view and the cover side view of the processor. Figure 23 shows the S.E.C.
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MECHANICAL SPECIFICATIONS Figure 23. S.E.C.
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MECHANICAL SPECIFICATIONS Figure 24. S.E.C.
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MECHANICAL SPECIFICATIONS Figure 25. SEC Cartridge Retention Enabling Details 1. Maximum protrusions of the mechanical heatsink attach media into cartridge during assembly or in an installed condition not to exceed 0.160” from external face of thermal plate. 2. Specified cover retention indent dimension is at the external end of the indent. Indent walls have 1.0degree draft, with the wider section on the external end. 3.
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MECHANICAL SPECIFICATIONS 7.1 Weight The maximum weight of a processor and thermal solution is approximately 500 grams. 7.2 Cartridge to Connector Mating Details The staggered edge connector layout makes the processor susceptible to damage from hot socketing (inserting the cartridge while power is applied to the connector). Extra care should be taken to ensure hot socketing does not occur.
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MECHANICAL SPECIFICATIONS Figure 28. Front View of Connector Mating Details NOTES: Retention devices for this cartridge must accommodate this cartridge “Float” relative to connector, without preload to the edge contacts in “X” and “Y” axes.
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MECHANICAL SPECIFICATIONS 7.3 Substrate Edge Finger Signal Listing Table 50 is the processor substrate edge finger listing in order by pin number. Table 51 is the processor substrate edge connector listing in order by pin name. These tables reflect the new SC330.1 pin definition, new or changed pins definitions are shown in bold. Table 50. Signal Listing in Order by Pin Number Pin No.
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MECHANICAL SPECIFICATIONS Table 50. Signal Listing in Order by Pin Number Pin No. Pin Name A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 VSS DEP#[5] DEP#[6] VSS D#[61] D#[55] VSS D#[60] D#[53] VSS D#[57] D#[46] VSS D#[49] D#[51] VSS VIN_SENSE VSS D#[42] D#[45] VSS D#[39] TEST_2.
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MECHANICAL SPECIFICATIONS Table 50. Signal Listing in Order by Pin Number Pin No.
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MECHANICAL SPECIFICATIONS Table 50. Signal Listing in Order by Pin Number Pin No.
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MECHANICAL SPECIFICATIONS Table 51. Signal Listing in Order by Pin Name Pin No.
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MECHANICAL SPECIFICATIONS Pin No.
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MECHANICAL SPECIFICATIONS Pin No.
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MECHANICAL SPECIFICATIONS Pin No. A159 A9 A7 B18 A151 B160 B161 B12 B15 B16 A18 A20 A23 A62 B27 A98 B4 A82 A24 B19 A130 B21 B100 B103 B11 B14 B17 B2 B20 B23 B26 B29 B32 B35 B38 B41 B44 B47 B5 B50 B53 B56 B58 B61 B64 B67 B70 B73 B76 B79 B8 B82 B85 B88 B91 B94 B97 B106 B109 Pin Name SA2 SELFSB0 SELFSB1 SLP# SMBALERT# SMBCLK SMBDAT SMI# STPCLK# TCK TDI TDO TEST_2.5_A23 TEST_2.5_A62 TEST_2.
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MECHANICAL SPECIFICATIONS Pin No.
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MECHANICAL SPECIFICATIONS Pin No.
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INTEGRATION TOOLS 8. INTEGRATION TOOLS The integration tool set for system designs will include an In-Target Probe (ITP) for program execution control, register/memory/IO access, and breakpoint control. This tool provides functionality commonly associated with debuggers and emulators. The ITP uses the on-chip debug features of the processor to provide program execution control.
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INTEGRATION TOOLS The ITP will connect to the system through the debug port. Recommended connectors, to mate the ITP cable with the debug port on the board, are available in either a vertical or right angle configuration. Both configurations fit into the same board footprint. The connectors are manufactured by AMP Incorporated and are in the AMPMODU System 50 line.
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INTEGRATION TOOLS Name RESET# Pin 1 Description Reset signal from MP cluster to ITP. Specification Requirement Terminate2 signal properly at the debug port. Debug port must be at the end of the signal trace. DBRESET# 3 Allows ITP to reset entire target system. Tie signal to target system reset (recommendation): PWR_OK signal on PCIset as an ORed input). Pulled-up signal with the proper resistor (see Signal Notes section, following). TCK 5 The TAP (Test Access Port) clock from ITP to MP cluster.
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INTEGRATION TOOLS Table 52. Debug Port Pinout Description and Requirements1 Name Pin Description Specification Requirement BSEN# 14 Informs target system that ITP is using boundary scan. PREQ0# 16 PREQ0# signal, driven by ITP, makes requests to P0 to enter debug. Add 150 to 330Ω pull-up resistor (to Vcc_TAP). PRDY0# 18 PRDY0# signal, driven by P0, informs ITP that P0 is ready for debug. Terminate2 signal properly at the debug port.
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INTEGRATION TOOLS NOTES: 1. 2. 3. Resistor values with “~” preceding them can vary from the specified value; use resistor as close as possible to the value specified. Termination should include series (~240Ω) and AGTL+ termination (connected to 1.5V) resistors. See Figure 30A. Signal should be at end of daisy chain and the boundary scan chain should be partitioned into two distinct sections to assist in debugging the system: one partition with only the processor(s) for system debug (i.e.
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INTEGRATION TOOLS The TDO signal of each processor has a 2.5V Tolerant open-drain driver. The TDI signal of each processor contains a 150Ω pull-up to VccTAP. When connecting one processor to the next, or connecting to the TDI of the first processor, no external pull-up is required. However, the last processor of the chain does require a pull-up before passing the signal to the next device in the chain. 8.1.6.
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INTEGRATION TOOLS NOTE The buffer rise and fall edge rates should NOT be FASTER than 3nS. Edge rates faster than this in the system can contribute to signal reflections that endanger ITP compatibility with the target system. A low voltage buffer capable of driving 2.5V outputs such as an 74LVQ244 is suggested to eliminate the need for attenuation. Simulation should be performed to verify that the edge rates of the buffer chosen are not too fast. The pull-up resistor to 2.
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BOXED PROCESSOR SPECIFICATIONS 9. BOXED PROCESSOR SPECIFICATIONS 9.1 Introduction The Pentium® III Xeon™ processor at 700 MHz and 900 MHz is also offered as an Intel® boxed processor. Intel® boxed processors are intended for system integrators who build systems from baseboards and off-theshelf components. The boxed Pentium® III Xeon™ processor at 700 MHz and 900 MHz is supplied with an attached passive heatsink.
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BOXED PROCESSOR SPECIFICATIONS A C D B Figure 34.
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BOXED PROCESSOR SPECIFICATIONS F E Figure 35. Front View Space Requirements for the Boxed Processor 9.2.1 BOXED PROCESSOR HEATSINK DIMENSIONS Table 53. Boxed Processor Heatsink Dimensions Fig. Ref. Label Dimensions (Inches) Min Typ A Heatsink Depth (off heatsink attach point) B Heatsink Height (above baseboard) C Heatsink Base Thickness D Heatsink Total Height at Fins 4.065 E Heatsink Total Height at Base (see front view) 4.235 F Heatsink Width (see front view) 5.05 Max 1.03 0.485 0.
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BOXED PROCESSOR SPECIFICATIONS processor does not require additional heatsink supports. processor. Heatsink supports are not shipped with the boxed 9.3 Thermal Specifications This section describes the cooling requirements of the heatsink solution utilized by the boxed processor. 9.3.1 Boxed Processor Cooling Requirements The boxed processor passive heatsink requires airflow horizontally across the heatsink to cool the processor.
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BOXED PROCESSOR SPECIFICATIONS Figure 36. Boxed Processor Heatsink Performance Figure 36 also shows the performance of the boxed processor heatsink with an attached auxiliary fan (50mm X 50mm X 15mm). In this case, the temperature of the air entering the fan is used as TAMBIENT. TAMBIENT is measured just outside the fan’s air intake. The presence of the auxiliary fan allows the cooling solution to perform with very little local airflow.
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BOXED PROCESSOR SPECIFICATIONS 4.24 1.5 Figure 38. Side View Space Recommendation for the Auxiliary Fan Figure 39. Front View Space Recommendation for the Auxiliary Fan 9.3.2.2 Fan power recommendations for auxiliary fan To facilitate power to the auxiliary fan and provide fan monitoring, a fan-sense capable power header may be provided on the baseboard near every processor that may need an auxiliary fan.
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BOXED PROCESSOR SPECIFICATIONS processor does not ship with an auxiliary fan, it is highly recommended that a power header be provided. It is also recommended that the power header be consistent with the power header for other boxed processors that feature a fan-sense capable fan heatsink. Figure 40 shows the typical boxed processor fan/heatsink power cable connector. Table 54 shows the typical boxed processor fan power cable connector requirements.
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APPENDIX 10. APPENDIX This appendix provides an alphabetical listing of all Pentium® III Xeon™ processor at 700 MHz and 900 MHz signals and tables that summarize the signals by direction: output, input, and I/O. 10.1 Alphabetical Signals Reference This section provides an alphabetical listing of all processor signals. 10.1.1 A[35:03]# (I/O) The A[35:3]# (Address) signals define a 236-byte physical memory address space.
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APPENDIX The BCLK (Bus Clock) is a 2.5V tolerant signal that determines the bus frequency. All processor system bus agents must receive this signal to drive their outputs and latch their inputs on the BCLK rising edge. All external timing parameters are specified with respect to the BCLK signal. 10.1.7 BERR# (I/O) The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error without a bus protocol violation.
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APPENDIX The BR[3:1]# (Bus Request) pins drive the BREQ[3:0]# signals on the system. The BR[3:0]# pins are interconnected in a rotating manner to other processors’ BR[3:0]# pins. Table 55 gives the rotating interconnect between the processor and bus signals for 4-way processor-based systems. Table 55.
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APPENDIX 10.1.17 DBSY# (I/O) The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the system bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on all processor system bus agents. 10.1.18 DEFER# (I) The DEFER# signal is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion.
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APPENDIX an external error signal (e.g. NMI) by system core logic. The processor will keep IERR# asserted until it is handled in software, or with the assertion of RESET#, BINIT#, or INIT#. 10.1.26 IGNNE# (I) The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to ignore a numeric error and continue to execute non-control floating-point instructions.
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APPENDIX 10.1.31 L2_SENSE On Pentium® III Xeon™ processor at 500 MHz and 550 MHz cartridges, L2_SENSE is routed from the edge of the connector pin B57 to the VL2 power plane. It allows monitoring the delivery of Vcc_L2 voltage at the L2 array device for this processor.
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APPENDIX specifications. Clean implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on, until they come within specification. The signal must then transition monotonically to a high (2.5V) state. Figure 41 illustrates the relationship of PWRGD to other system signals. PWRGD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGD.
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APPENDIX Pull-up for Pentium® III Xeon™ Processor 3V->5V buffer (7408) 3.3V 5V Vcc_smb(3.3V) +5V OCVR VRM OCVR_EN OUTEN PWRGD OCVR_EN OCVR_OK 3.3V 5V PWR_GD_PS Other PS’s, VRMs, OCVRs with open-drain PWR_GDs OCVR_OK CPU_PWR_GD CPU_PWRGD CPU_RESET# Delay Processor Core Reset Logic Figure 42. PWRGD Implementation 10.1.41 REQ[4:0]# (I/O) The REQ[4:0]# (Request Command) signals must connect the appropriate pins of all processor system bus agents.
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APPENDIX 10.1.42 RESET# (I) Asserting the RESET# signal resets all processors to known states and invalidates their L1 and L2 caches without writing back any of their contents. RESET# must remain active for one microsecond for a "warm" reset; for a power-on reset, RESET# must stay active for at least one millisecond after the PWRGOOD input to the processor has asserted; until this de-assertion of RESET# occurs, all outputs from the processor are indeterminate unless otherwise specified.
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APPENDIX 10.1.47 SELFSB0 (I) SELFSB1 (O) The Pentium® III Xeon™ processor at 700 MHz and 900 MHz adds a definition to the SELFSB [1:0] pins which is compatible with legacy systems as well as new platforms. The added functionality provides the means for the clock synthesizer and additional baseboard logic to auto detect the expected system bus frequency required by a specific cartridge. Table 59 and Figure 43 provide a summary of the functionality and the resistor values for an frequency auto detect circuit.
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APPENDIX Table 59. Description of SELFSB pins processor Pin Location Pentium® III Xeon™ processor at 700 MHz and 900 MHz Pentium® III Xeon™ processor at 500 MHz and 550 MHz & Pentium® II Xeon™ processor Pin Name A7 Functionality SELFSB1 Output, Frequency Detect A9 SELFSB0 A7 A9 Vss Reserved Input, Frequency Selection. None None SELFSB1: Output, (Frequency Detect). 100 MHz = GND. SELFSB0: Pentium® III Xeon™ processor at 500 MHz and 550 MHz: Not used..
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APPENDIX The SMBCLK (SMBus Clock) signal is an input clock to the system management logic which is required for operation of the system management features of the Pentium® III Xeon™ processor at 700 MHz and 900 MHz. This clock is asynchronous to other clocks to the processor. 10.1.51 SMBDAT (I/O) The SMBDAT (SMBus DATA) signal is the data signal for the SMBus. This signal provides the single-bit mechanism for transferring data between SMBus devices. 10.1.
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APPENDIX 10.1.60 TRDY# (I) The TRDY# (Target Ready) signal is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all processor system bus agents. 10.1.61 TRST# (I) The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. The processor self-resets during power on; therefore, it is not necessary to drive this signal during power on reset. 10.1.
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APPENDIX Table 61.
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APPENDIX Table 62.