User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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9.4.7. AR14

Color Select Register
I/O (and Memory Offset) Address: Read at 3C1h and Write at 3C0h; (index=14h)
Default: 0Uh (U=Undefined)
Attributes: Read/Write
7 4 3 2 1 0
Reserved (0000) P7 P6 Alt P5 Alt P4
Bit Description
7:4 Reserved.
3:2 Palette Bits P[7:6]. These are the 2 upper-most of the 8 bits that are used to map either text attributes
or pixel color input values (for modes that use 16 colors) to the 256 possible colors contained in the
palette. These 2 bits are common to all 16 sets of bits P5 through P0 that are individually supplied by
Palette Registers 0-F (AR[00:0F]).
1:0 Alternate Palette Bits P[5:4]. These 2 bits can be used as an alternate version of palette bits P5 and
P4. Unlike the P5 and P4 bits that are individually supplied by Palette Registers 0-F (AR[00:0F]), these
2 alternate palette bits are common to all 16 of Palette Registers. Bit 7 of the Mode Control Register
(AR10) is used to select between the use of either the P5 and P4 bits that are individually supplied by
the 16 Palette Registers or these 2 alternate palette bits.
9.5. VGA Color Palette Registers
The palette DAC has two main components: a palette in which a selection of 256 colors may be stored,
and a set of three digital to analog (D-to-A) converters, one each for the red, green and blue components
used to produce a color on a CRT display. The palette DAC is also frequently called the RAMDAC, to
emphasize the presence of memory alongside the three D-to-A converters, and the palette, itself, is often
referred to as the CLUT or color look-up table.
During normal use, the palette DAC is operated either in direct-color mode or indexed-color mode.
Direct color mode is used with pixel depths of 15, 16, or 24 bits per pixel. In direct color mode, the pixel
data received from the frame buffer, through the sequencer and the attribute controller, directly specifies
the color for a given pixel. This pixel data is pre-formatted such that certain bits of the pixel data for each
pixel are used to provide the red, green and blue output values for each of the three corresponding 8-bit
D-to-A converters. Indexed-color mode is used with pixel depths of 8 bits per pixel or less. In indexed-
color mode, the incoming pixel data for each pixel is actually an 8-bit index that is used to choose one of
the 256 color data positions within the palette. Each color data position holds a 24-bit color value that
specifies the actual 8-bit red, green, and blue values for each of the three corresponding 8-bit D-to-A
converters. In essence, the colors for each pixel are specified indirectly, with the actual choice of colors
taking place in the color data positions of the palette, while the incoming pixel data chooses from among
these color data positions. This method allows the full range of over 16 million possible colors to be
accessible in modes with only 8 or fewer bits per pixel.
The color data stored in these 256 color data positions can be accessed only through a complex sub-
addressing scheme, using a data register and two index registers. The Palette Data Register at I/O address
3C9h (or memory address offset 3C1h) is the data port. The Palette Read Index Register at I/O address
3C7h (or memory address offset 3C7h) and the Palette Write Index Register at I/O address 3C8h (or
memory address offset 3C8h) are the two index registers. The Palette Read Index Register is used to
choose the color data position that is to be read from the data port. The Palette Write Index Register is