User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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9.5.2. DACSTATE

DAC State Register
I/O (and Memory Offset) Address: 3C7h
Default: 00h
Attributes: Read Only
7 2 1 0
Reserved (000000) DAC State
Bit Description
7:2 Reserved. Read as 0s.
1:0 DAC State. This field indicates which of the two index registers was most recently written.
Bits [1:0] Index Register Indicated
00 Palette Write Index Register at I/O Address 3C7h (default)
01 Reserved
10 Reserved
11 Palette Read Index Register at I/O Address 3C8h
9.5.3. DACRX

Palette Read Index Register
I/O (and Memory Offset) Address: 3C7h
Default: 00h
Attributes: Write Only
Bit Description
7:0 Palette Read Index. The 8-bit index value programmed into this register chooses which of 256 standard
color data positions within the palette (or which of 8 alternate color data positions, depending on the
state of a bit in the Pixel Pipeline Control 0 Register) are to be made accessible for being read via the
Palette Data Register (DACDATA). The index value held in this register is automatically incremented
when all three bytes of the color data position selected by the current index have been read.
9.5.4. DACWX

Palette Write Index Register
I/O (and Memory Offset) Address: 3C8h
Default: 00h
Attributes: Write Only
Bit Description
7:0 Palette Write Index. The 8-bit index value programmed into this register chooses which of 256 standard
color data positions within the palette (or which of 8 alternate color data positions, depending on the
state of a bit in the Pixel Pipeline Control 0 Register) are to be made accessible for being written via the
Palette Data Register (DACDATA). The index value held in this register is automatically incremented
when all three bytes of the color data position selected by the current index have been written.