User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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116
Bit Description
3 Vertical Blanking Start Bit 8. The vertical blanking start is a 10-bit or 12-bit value that specifies the
beginning of the vertical blanking period relative to the beginning of the active display area.
In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical blanking
start is specified with a 10-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of
the Vertical Blanking Start Register (CR15), and the most and second-most significant bits are supplied
by bit 5 of the Maximum Scan Line Register (CR09) and this bit of this register, respectively.
In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the vertical blanking start
is specified with a 12-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of the
Vertical Blanking Start Register (CR15), and the 4 most significant bits are supplied by bits [3:0] of the
Extended Vertical Blanking Start Register (CR33). In extended modes, neither this bit, nor bit 5 of the
Maximum Scan Line Register (CR09) are used.
This 10-bit or 12-bit value should be programmed to be equal to the number of scan line from the
beginning of the active display area to the beginning of the blanking period. Since the active display
area always starts on the 0th scan line, this number should be equal to the number of the scan line on
which the vertical blanking period begins.
2 Vertical Sync Start Bit 8. The vertical sync start is a 10-bit or 12-bit value that specifies the beginning
of the vertical sync pulse relative to the beginning of the active display area.
In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical sync start
is specified with a 10-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of the
Vertical Sync Start Register (CR10), and the most and second-most significant bits are supplied by bit 7
and this bit, respectively, of this register.
In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the vertical display end is
specified with a 12-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of the
Vertical Sync Start Register (CR10), and the 4 most significant bits are supplied by bits [3:0] of the
Extended Vertical Sync Start Register (CR32) register. In extended modes, neither this bit, nor bit 7 of
this register are used.
This 10-bit or 12-bit value should be programmed to be equal to the number of scan lines from the
beginning of the active display area to the start of the vertical sync pulse. Since the active display area
always starts on the 0th scan line, this number should be equal to the number of the scan line on which
the vertical sync pulse begins.
1 Vertical Display Enable End Bit 8. The vertical display enable end is a 10-bit or 12-bit value that
specifies the number of the last scan line within the active display area.
In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical display
enable end is specified with a 10-bit value. The 8 least significant bits of this value are supplied by bits
[7:0] of the Vertical Display Enable End Register (CR12), and the most and second-most significant bits
are supplied by bit 6 and this bit, respectively, of this register.
In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the vertical display enable
end is specified with a 12-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of
the Vertical Display Enable End Register (CR12), and the 4 most significant bits are supplied by bits
[3:0] of the Extended Vertical Display End Enable Register (CR31). In extended modes, neither this bit,
nor bit 6 of this register are used.
This 10-bit or 12-bit value should be programmed to be equal to the number of the last scan line within
in the active display area. Since the active display area always starts on the 0th scan line, this number
should be equal to the total number of scan lines within the active display area, minus 1.