User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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118
9.6.11. CR09

Maximum Scan Line Register
I/O (and Memory Offset) Address: 3B5h/3D5h (index=09h)
Default: 00h
Attributes: Read/Write
7 6 5 4 0
Double
Scanning
Line Cmp
Bit 9
Vert Blnk
Start Bit 9
Starting Row Scan Count
Bit Description
7 Double Scanning Enable.
0 = Disable. When disabled, the clock to the row scan counter is equal to the horizontal scan rate. This
is the normal setting for many of the standard VGA modes and all of the extended modes.
1 = Enable. When enabled, the clock to the row scan counter is divided by 2. This is normally used to
allow CGA-compatible modes that have only 200 scan lines of active video data to be displayed as
400 scan lines (each scan line is displayed twice).
6 Line Compare Bit 9. This bit provides the most significant bit of a 10-bit value that specifies the scan
line at which the memory address counter restarts at the value of 0. Bit 4 of the Overflow Register
(CR07) supplies the second most significant bit, and bits 7-0 of the Line Compare Register (CR18)
supply the 8 least significant bits.
Normally, this 10-bit value is set to specify a scan line after the last scan line of the active display area.
When this 10-bit value is set to specify a scan line within the active display area, it causes that scan line
and all subsequent scan lines in the active display area to display video data starting at the very first
byte of the frame buffer. The result is what appears to be a screen split into a top and bottom part, with
the image in the top part being repeated in the bottom part.
When used in cooperation with the Start Address High Register (CR0C) and the Start Address Low
Register (CR0D), it is possible to create a split display, as described earlier, but with the top and bottom
parts displaying different data. The top part will display whatever data exists in the frame buffer starting
at the address specified in the two aforementioned start address registers, while the bottom part will
display whatever data exists in the frame buffer starting at the first byte of the frame buffer.
5 Vertical Blanking Start Bit 9. The vertical blanking start is a 10-bit or 12-bit value that specifies the
beginning of the vertical blanking period relative to the beginning of the active display area.
In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical blanking
start is specified with a 10-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of
the Vertical Blanking Start Register (CR15), and the most and second-most significant bits are supplied
by this bit and bit 3 of the Overflow Register (CR09), respectively.
In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the vertical blanking start
is specified with a 12-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of the
Vertical Blanking Start Register (CR15), and the 4 most significant bits are supplied by bits [3:0] of the
Extended Vertical Blanking Start Register (CR33). In extended modes, neither this bit, nor bit 3 of the
Overflow Register (CR09) are used.
This 10-bit or 12-bit value should be programmed to be equal to the number of scan line from the
beginning of the active display area to the beginning of the blanking period. Since the active display
area always starts on the 0th scan line, this number should be equal to the number of the scan line on
which the vertical blanking period begins.
4:0 Starting Row Scan Count. This field provides all 5 bits of a 5-bit value that specifies the number of scan
lines in a horizontal row of text. This value should be programmed to be equal to the number of scan lines
in a horizontal row of text, minus 1.