User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
128
Bit Description
3 Count By 2. This bit is used in conjunction with bit 5 of the Underline Location Register (CR14) to select
the number of character clocks are required to cause the memory address counter to be incremented.
0 = The memory address counter is incremented either every character clock or every 4 character
clocks, depending upon the setting of bit 5 of the Underline Location Register.
1 = The memory address counter is incremented either every other clock.
CR14[5] CR17[3] Address Incrementing Interval
0 0 every character clock
0 1 every 2 character clocks
1 0 every 4 character clocks
1 1 every 2 character clocks
2 Horizontal Retrace Select. This bit provides a way of effectively doubling the vertical resolution by
allowing the vertical timing counter to be clocked by the horizontal retrace clock divided by 2 (usually, it
would be undivided).
0 = The vertical timing counter is clocked by the horizontal retrace clock.
1 = The vertical timing counter is clocked by the horizontal retrace clock divided by 2.
1 Select Row Scan Counter.
0 = A substitution takes place, where bit 14 of the 16-bit memory address generated of the memory
address counter (after the stage at which these 16 bits may have already been shifted to
accommodate word or DWord addressing) is replaced with bit 1 of the row scan counter at a stage
just before this address is presented to the frame buffer address decoder.
1 = No substitution takes place. See following tables.
0 Compatibility Mode Support.
0 = A substitution takes place, where bit 13 of the 16-bit memory address generated of the memory
address counter (after the stage at which these 16 bits may have already been shifted to
accommodate word or DWord addressing) is replaced with bit 0 of the row scan counter at a stage
just before this address is presented to the frame buffer address decoder.
1 = No substitution takes place. See following tables.
The following tables show the possible ways in which the address bits from the memory address counter
can be shifted and/or reorganized before being presented to the frame buffer address decoder. First, the
address bits generated by the memory address counter are reorganized, if need be, to accommodate byte,
word or DWord modes. The resulting reorganized outputs (MAOut15-MAOut0) from the memory
address counter may also be further manipulated with the substitution of bits from the row scan counter
(RSOut1 and RSOut0) before finally being presented to the input bits of the frame buffer address
decoder (FBIn15-FBIn0).