User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

133

9.6.30. CR31



Extended Vertical Display End Register

I/O (and Memory Offset) Address: 3B5h/3D5h (index=31h)

Default: 00h

Attributes: Read/Write

7 4 3 0

Reserved (0000) Vertical Display End Bits 11:8

Bit Description

7:4 Reserved. Read as 0s. This field must be 0s when this register is written.

3:0 Vertical Display End Bits [11:8]. The vertical display enable end is a 10-bit or 12-bit value that

specifies the number of the last scan line within the active display area.

In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical display

enable end is specified with a 10-bit value. The 8 least significant bits of this value are supplied by bits

[7:0] of the Vertical Display Enable End Register (CR12), and the 2 most significant bits are supplied by

bits 6 and 1 of the Overflow Register (CR07). In standard VGA modes these 4 bits of this register are

not used.

In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the vertical display enable

end is specified with a 12-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of

the Vertical Display Enable End Register (CR12), and the 4 most significant bits are supplied by these 4

bits of this register.

This 10-bit or 12-bit value should be programmed to be equal to the number of the last scan line within

in the active display area. Since the active display area always starts on the 0th scan line, this number

should be equal to the total number of scan lines within the active display area, minus 1.