User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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10.5.3. 3D Instructions
The 3D instructions are used to program the 3D pipeline state and perform 3D, Stretch Blt, and
MotionComp operations. All 3D state instructions are of fixed length, while the rendering instructions
are all variable length. Refer to the Rendering Engine Instruction Chapter for a description of the 3D
instructions.
Figure 29. Instruction Format For First DWord
Bits
TYPE 31:29 28:24 23 22 21:0
Parser 000 Opcode
00h – NOP
0Xh – Single DWord Packets
1Xh – Two DWord Packets
2Xh – Store DWord Packets
3Xh – Ring/Batch Buffer Pkts
Identification No./DWord Count
Instruction Dependent Data
5:0 – DWord Count
5:0 – DWord Count
5:0 – DWord Count
Rsvd. 001
2D 010 Opcode Instruction Dependent
Data
4:0 – DWord Count
3DState24 011 Opcode – 00000–01111 Instruction Dependent Data
23:0 – 24 state and mask bits
3DState24NP 011 Opcode – 10000–11000 Instruction Dependent Data
23:0 – 24 non-pipelined state and mask bits
Rsvd 011 Opcode – 11001–11011
3DState16 011 Opcode – 11100 23:19
Sub Opcode
00h–7Fh
18:16 –
Texture
Map.
15:0 – 16
state and
mask bits
3DState16NP 011 Opcode – 11100 23:19
Sub Opcode
80h–FFh
18:16 –
Scissor
Rect. No.
15:0 – 16
state and
mask bits
3DStateMW
(Multiple
DWord)
011 Opcode – 11101 23:16
Sub Opcode
00h–7Fh
15:0 – DWord Count
3DStateMWNP
(Multiple
DWord)
011 Opcode – 11101 23:16
Sub Opcode
80h–FFh
15:0 – DWord Count
3DBlock 011 Opcode – 11110 23:16
Sub Opcode
15:0 – DWord Count
3DPrim 011 Opcode – 11111 23:16
Sub Opcode
17:0 – DWord Count
Reserved 1XX
NOTES:
1. SrcCopyImmBlt does not follow the 2D format.
2. The qualifier “NP” indicates that the state variable is non-pipelined and the render pipe is flushed before such a
state variable is updated. All the other state variables are pipelined (default).