User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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12.2.13. FULL_BLT
The full BLT is the most comprehensive BLT instruction. It provides the ability to specify all 3
operands: destination, source, and pattern. The source and pattern operands are the same bit width as the
destination operand.
The whole color pattern (8 x 8 pixels = 8, 16, or 64 DWs) is read at the beginning of the BLT and stored
in the Texture Cache. The pattern vertical alignment specifies which scan line of the pattern is used first.
The destination address specifies the horizontal alignment The only memory accesses required for the
remainder of the BLT is source and destination accesses.
Both the source and destination pitches can be either sign. The pattern direction follows the destination
operand.
The Intel
®
815 chipset hardware has a restriction that the BLT color source and destination operands
must not co-exist on the same 32-Byte cacheline. To work-around this issue :
For BLTs that have sharing of a cacheline for a given scanline, the driver must treat this as an
overlapping BLT case.
For linear memory, the surfaces allocated must be 32B-cacheline aligned.
DWord Bit Description
0 = BR00 31:29 Client : 02h – 2D Processor
28:22 Instruction Target (Opcode) : 45h
21:11 Reserved. Must be Zero
10:08 Destination Transparency Mode: See BR00 definition.
07:05 Pattern Vertical Alignment: (which scan line of the 8x8 pattern to start on)
04:00 Dword Length : 06h
1 = BR13 31 Reserved. Must be Zero
30 X Direction: (1 = written from right to left (decrementing = backwards);
0 = incrementing)
29:28 Reserved. Must be Zero
27 Reserved. Must be Zero
26 Must Be One (‘1’).
25:24 Color Depth:
00 = 8 bit color
01 = 16 bit color
10 = 24 bit color
11 = reserved
23:16 Raster Operation:
15:00 Destination Pitch (signed): (13:00 are implemented in Intel
®
810 chipset)
2 = BR14 31:16 Destination Height (in scan lines): (28:16 are implemented in Intel
®
810 chipset)
15:00 Destination Width (in bytes): (12:00 are implemented in Intel
®
810 chipset)