User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
19
• Support for a single processor configuration
• 64-bit AGTL+ based System Bus Interface at 66/100/133 MHz
• 32-bit Host Address Support
• 64-bit System Memory Interface with optimized support for SDRAM at 100/133 MHz
• Integrated 2D & 3D Graphics Engines
• Integrated H/W Motion Compensation Engine
• Integrated 230 MHz DAC
• Integrated Digital Video Out Port
• 133 MHz Display Cache
• AGP 1X/2X/4X Controller
Figure 2. Intel
®
82815 Chipset GMCH Block Diagram
System Bus Interface
Buffer
Memory Interface
Buffer
Hub Interface
System
Memory
HW Motion Comp
Display Engine 3D Engine
3D
Engine
DAC Overlay
HW Cursor
Digital Video Out
Port
2D Engine
Stretch
BLT Eng
BLT Eng
Analog
Display
Out
Digital
Video
Out
DDC/
I
2
C
gmch_blk2.vsd
AGP Interface
Local Memory
Interface
AGP/
Display
Cache
Pins
2.2.1. Host Interface
The host interface of the GMCH is optimized to support the Intel

Pentium
®
III processor and Intel

Celeron
TM
processor in the FC-PGA package. The GMCH implements the host address, control, and data
bus interfaces within a single device. The GMCH supports a 4-deep in-order queue (i.e., supports
pipelining of up to 4 outstanding transaction requests on the host bus). Host bus addresses are decoded
by the GMCH for accesses to system memory, PCI memory and PCI I/O (via hub interface), PCI
configuration space and Graphics memory. The GMCH takes advantage of the pipelined addressing
capability of the processor to improve the overall system performance.
The Intel
®
82815 chipset GMCH supports the 370-pin socket processor.