User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
218
Discrete
Device
Integrated
Device
Base
Address Bits
[31:26]
Utilize Fence
Registers
Fence
Range Hit
Tiled
Surface
Tile
Walk
Surface
✔ ✔ All Zeros Yes No ⊗ ⊗ Linear
✔ ✔ All Zeros Yes Yes ⊗ ⊗ Tiled
*
✔ All Zeros No ⊗ No ⊗ Linear
✔ All Zeros No ⊗ Yes ✔ Tiled
✔ Any Bit Set ⊗ ⊗ No ⊗ Linear
✔ Any Bit Set ⊗ ⊗ Yes ✔ Tiled
* The pitch specified in this instruction must be the same as the pitch in the corresponding fence register
Surfaces that contain mip-maps are located within a single rectangular area of memory identified by the
base address of the upper left corner and a pitch. The pitch must be specified at least as large as the next
power of two, equal to or greater than the widest mip-map. These surfaces may be overlapped in memory
and must adhere to the following memory organization rules:
• The Base Address must be 4 KB aligned.
• Each successively smaller mip-map must lie vertically below and left aligned.
• Each mip-map must have its upper left corner vertically aligned to an even quadword address.
The following figures show an example of a 32x8 @ 16 bpt and a 4x8 @ 16 bpt map where the dashed
lines identify quadwords.
Figure 34 Mip-map Surface Organization Example
32x8
16x4
8x2
4x1
2x1
1x1
Base Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
4x8
2x4
1x2
1x1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15