User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
252
DWord Bit Description
1 31:24 Reserved: 00h
23:20 Destination Origin Horizontal Bias: This is an unsigned value (0.4) that is used to
bias the origin of the X values associated with the vertices of a primitive. The unbiased
origin is located in the upper-left corner of a square pixel with the center located at 0.5,
0.5. A bias value of ½ (8h) would move the origin toward the right, such that an X value
of 0.0 would specify the center of a pixel.
19:16 Destination Origin Vertical Bias: This is an unsigned value (0.4) which is used to
bias the origin of the Y values associated with the vertices of a primitive. The unbiased
origin is located in the upper-left corner of a square pixel/texel with the center located at
0.5, 0.5. A bias value of ½ (8h) would move the origin toward the bottom, such that a Y
value of 0.0 would specify the center of a pixel/texel.
15:14 Reserved: 00h
13:12 4:2:2 Channel Write Select: Select which channel(s) are written to the destination
buffer when the surface format is 4:2:2 using byte masks.
00 = Write all channels (Y,Cr, and Cb)
01 = Write only the Y channel
10 = Write only the Cr channel
11 = Write only the Cb channel
11 Reserved (Additional Buffer Formats)
10:8 Dest Buffer Format:
0h = Any 8-bit Surface
1h = RGB 555 (16th bit is written as 0)
2h = RGB 565
3h = Reserved (ARGB 8888)
4h = 4:2:2 YCrCb (Y Swap format in memory)
5h = 4:2:2 YcrCb (Normal format in memory)
6h = 4:2:2 YcrCb (UV Swap format in memory)
7h = 4:2:2 YcrCb (UV/Y Swap format in memory)
7:2 Reserved: 00h
1 Vertical Line Stride: The number of lines to skip between logically adjacent lines.
0 = Do not skip any lines.
1 = Skip 1 line. (provides support for Interleaved/field surfaces)
0 Vertical Line Stride Offset: The number of lines to add as an initial offset when the
Vertical Line Stride is 1.
0 = Add no offset. (top field)
1 = Add 1. (bottom field)