User's Manual
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
254
3D instruction GFXRENDERSTATE_BOOLEAN_EN_2. To ensure proper hardware operation,
software must follow up with the GFXCMDPARSER_FLUSH instruction to cause the hardware to
flush the 3D pipeline.
Color Calculator
• Texture blend stage 0 must always be enabled. For untextured primitives, a select arg operation
should be programmed. This is equivalent to a pass through operation to the next pipeline stage.
• When Stage N is enabled, Stages 0:(N-1) should also be enabled.
• Current (as opposed to accumulator) must be selected as output for the last enabled stage.
• Data must be written to Current output register before it is selected as an input argument for the next
stage.
• Data must be written to Accumulator output register before it is selected as an input argument for a
later stage.
• Replicate α in specular is not allowed.
• Current α cannot be used for blending.
Stretch BLT
• When doing stretch BLT in YUV 422 format, the origin of the source rectangle must be DWord
aligned. In other words, the X coordinate of the origin must be even.
Texture/Color/Z Surface Pitch
• Texture surface pitch
1
== Pitch of tiled region (programmed in fence register).
• Texture surface pitch must be ≥ 4 QWs for linear organization of memory.
i.e. MAP_INFO_DW1[3:0] ≥ 2h
• Texture surface pitch must be ≥ 16 QWs for Tiled organization of memory.
i.e. MAP_INFO_DW1[3:0] ≥ 4h
• Texture surface pitch (in bytes) must be ≥ Map_Width (in bytes)
i.e. 8 * 2
MAP_INFO_DW1[3:0]
≥ 2
MAP_INFO_DW2[3:0]
(pow2mapsize == 1)
8 * 2
MAP_INFO_DW1[3:0]
≥ MAP_INFO_DW2[9:0] (pow2mapsize == 0)
• Texture base address (MAP_INFO_DW3[26:4]) must be QW aligned. Also,
2n * surface pitch ≤ texture base address < (2n+1) surface pitch.
• Color Pitch and Z Pitch
2
== Pitch of tiled region.
• Only Bit(26:4) in the Texture Map Base Address are used in texture address calculation.
Context 1
• No state variable pipelining in Context 1. Change of state variables required a pipeline flush.
• No Multi-TX in context 1. Only texel 0 is available.
1
The texture surface pitch (MAP_INFO_DW1[3:0] ) is expressed in terms of log
2
(pitch in QWs).
2
The Color/Z pitch (DEST_BUFFER_INFO_DW2[1:0]/ Z_BUFFER_INFO_DW1[1:0]) is expressed in terms of log
2
(pitch in QWs/64).