User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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14.5. LCD_CLKD—LCD Clock Divisor Register
Address Offset: 0600Ch–0600Fh
Default Value: 00030013h
Attribute: R/W
Size: 32 bits
The LCD Clock Divisor register and Display & LCD Clock Divisor Select Register are programmed
with the loop parameters to be loaded into the clock synthesizer.
Data is written to LCD Clock Divisor register followed by a write to the LCD Clock byte of the Display
& LCD Clock Divisor Select Register. The completion of the write to the Display & LCD Clock
Divisor Select Register causes data from both registers to transfer to the VCO register file simultane-
ously. This prevents wild fluctuations in the VCO output during intermediate stages of a clock
programming sequence.
31 26 25 16 15 10 9 0
Reserved VCO LCD N-Divisor Reserved VCO LCD M-Divisor
Bit Description
31:6 Reserved.
25:16 VCO LCD N-Divisor. N-Divisor value calculated for the desired output frequency. (default = 03h)
15:10 Reserved.
9:0 VCO LCD M-Divisor. M-Divisor value calculated for the desired output frequency. (default = 13h)