User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

264

14.7. PWR_CLKC—Power Management and Miscellaneous

Clock Control

Address Offset: 6014h–06017h

Default Value: 0000 0101 h

Attribute: R/W

Size: 32 bits

31 17 16

Reserved

15 12 11 10 9 8

Reserved

7 2 1 0

Reserved Display

Clock PLL

VCO

Internal

DAC

Enable

Bit Description

31:2 Reserved.

1 Display Clock PLL VCO

0 = Enable (default)

1 = Disable

0 Internal DAC Enable.

0 = Disables the internal DAC (PowerDown). If HSYNC/VSYNCControl[0] = 0, disables HSYNC and

VSYNC.

1 = Enables the internal DAC and does not allow disable of HSYNC and VSYNC via HSYNC/VSYNC

Control[0]. (default)