User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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15. Overlay Registers
This chapter contains the Overlay and Gamma Correction registers and an Overlay instruction. The
current graphics controller implements one overlay that is referred to as Overlay 0. Note that the Overlay
0 control registers are indirectly written by first setting up a buffer in memory and then instructing the
graphics controller to update the on-chip registers from this buffer. Software can invoke the update
process by writing to the OV0ADD register or by issuing the Overlay Flip instruction. Note that the
Gamma Correction registers are read/written directly. The register/instruction categories are listed in the
Overlay Register/Instruction Categories table.
Note: The Intel
®
815 chipset does not support overlay for low display resolution modes. Thus, the overlay is
not supported for all resolution modes smaller than 640x480.
overlay1.vsd
(Base = MMADR PCI Reg.)
System Memory
base+301xxh
Overlay 0 Reg
Graphics Controller
Register Range
(512 KB)
Graphics Memory
Base+xxh
(Base = OV0ADD Reg.)
Overlay 0 Reg
On-chip registers for Overlay 0
(read only; debug)
Memor
y
buffer area for loadin
g
on-chip r
e
- Software setsup register values
- HW updates on-chip re
g
s for next VBL
A
Do not use the “Wait for VBLANK” mechanism to force a sequence of overlay flips. Use the “Wait for
Scan Lines” mechanism with the scan line set up to be at least 1 scan line after vertical blank start to
force the loading of the next Overlay x Register Update Address which will take effect after the next
displayed overlay frame.