User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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15.2. DOV0STA—Display/Overlay 0 Status Register
Memory Address Offset: 30008h–3000Bh
Default Value: 0000 5000h
Access: RO
Size: 32 bits
This read-only register indicates the status for the overlay. References to display are either the primary
timing generator or the secondary timing generator depending on which is currently being used.
31 30 24
Reg
Update
Status
Reserved
23 21 20 19 18 15
Reserved Overlay 0 Current
Buffer/Field.
Reserved
14 13 12 11 10 0
Not Active
Pixel
Reserved Not Active
Video
Scan Line
Reserved Display Line Status.
Bit Description
31 Register Update Status. All registers latched (Flip Pending = 0).
vblank
vblank
status bit
status bit
overlay registers are updated
overlay update register has been written
overlay update register has been written
overlay registers are updated
overlay registers are updated
overlay update register has been written
0 = overlay registers have been updated.
1 = overlay update register has been written, overlay registers have not been updated.
30:21 Reserved.