User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
274
15.4. Memory Offset Registers
15.4.1. Overlay Buffer Pointer Registers
These registers provide address pointers into the system memory or Local memory buffer areas. The
buffers must be QWord aligned. Pixel panning on a pixel basis is done using the byte addresses. Overlay
buffers need to be QWord aligned and the stride should be a QWord multiple. Buffer pointers should
always be aligned to the natural boundaries based on the data format. For planar formats (YUV410,
YUV420), the Y and UV pointers should be naturally aligned to each other. Their natural alignment
depends on the particular data format.
Alignment Format
Pixels Bytes
RGB packed 1 2
YUV 4:2:2 packed 2 4
YUV 4:1:1 packed 8 12
YUV Planar 1 1
Only the Register Update Address register should be written while the overlay is active. Otherwise,
values will be loaded by writing the register image into memory and writing the command register with
the address of the memory image in the Register Update address.
15.4.1.1. OBUF_0Y—Overlay Buffer 0 Y Pointer Register
Memory Buffer Address Offset: 00h (R/W)
On-chip Reg. Mem Addr Offset: 30100h (RO; debug path)
Default Value: 00h
Access: see address offset above
Size: 32 bits
31 26 25 0
Reserved Overlay Buffer 0 Y Pointer
Bit Description
31:26 Reserved.
25:0 Overlay Buffer 0 Y Pointer. For Y Planar or packed color data (byte address). Must be pixel aligned
(low order bit zero for 16-bpp packed formats). When mirroring horizontally (X backwards), this points
to the last byte of the line.