User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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15.4.10. Overlay Configuration Registers
There is only 1 Overlay Configuration register which controls both overlay streams. It is read from
memory with Overlay 0 register loads during Vertical Blank.
15.4.10.1. OV0CONF—Overlay Configuration Register
Memory Address Offset: 64h (R/W)
On-chip Reg. Mem Addr Offset: 30164h (RO; debug path)
Default Value: 00h
Access: see address offset above
Size: 32 bits
31 8
Reserved
7 6 5 4 3 1 0
Reserved Cr Cb
Rdjust En
(Reserved)
Reserved YUV Conv
En
(Reserved)
Reserved Line Buf
Conf
Bit Description
31:7 Reserved.
6 Cr Cb Readjust Enable. (Reserved Field in Intel
®
810 Chipset. Reserved for future
implementations.)
0 = Disable Cr Cb Readjust
1 = Enable Cr Cb Readjust (TV-Out mode = convert back to U,V = excess 128 and Y=Y+16)
5 Reserved.
4 YUV Conversion Enable. (Reserved for future implementations.) The conversion disabled setting
should only be used when the overlay data is being directed out to the video side port.
0 = Enable YUV Conversion
1 = Disable YUV Conversion (TV-Out: YUV 4:4:4) mode
3:1 Reserved.
0 Line Buffer Configuration. Sets the line buffer configuration:
0 = 2 720 pixel line buffers
1 = 1 1440 pixel line buffer