User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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15.4.12.2. AWINSZ—Alpha Blend Window Size Register
Memory Address Offset: 74h (R/W)
On-chip Reg. Mem Addr Offset: 30174h (RO; debug path)
Default Value: 00h
Access: see address offset above
Size: 32 bits
31 27 26 16 15 11 10 0
Reserved Alpha Blend Vertical
Size
Reserved Alpha Blend Horizontal
Size
Bit Description
31:27 Reserved.
26:16 Alpha Blend Vertial Size. Determines where on the display screen coordinates the overlay display are
alpha blended. Alpha Blend Vertical Size in lines (never specifies scan lines off the active display)
15:11 Reserved.
10:0 Alpha Blend Horizontal Size. Determines where on the display screen coordinates the overlay
display are alpha blended. Alpha Blend Horizontal Size in pixels (never specifies pixels off the active
display)
15.5. Overlay Flip Instruction
DWord Bit Description
0 31:29 Client: xxh
28:23 Function Index:
22:16 Instruction Target
1 31:0 Register Update Address:
Do not use the “Wait for VBLANK” mechanism to force a sequence of overlay flips. Use the “Wait for
Scan Lines” mechanism with the scan line set up to be at least 1 scan line after vertical blank start to
force the loading of the next Overlay x Register Update Address which will take effect after the next
displayed overlay frame. For Intel
®
810 chipset, the Overlay Update Address register can be loaded
either before or after the “Wait for VBLANK” (primary display VBLANK). Future implementations
should create a “Wait for Overlay Flip Not Pending” mechanism if this becomes an issue, especially
since the Overlay may not use the primary display’s timing generator in the future.