User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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3.1. Memory and I/O Space Registers
This section provides a high-level register map (register groupings per function). The memory and I/O
maps for the GC registers are shown in the following figure. The VGA and Extended VGA registers can
be accessed via standard VGA I/O locations as well as via memory-mapped locations. In addition, the
memory map contains allocation ranges for various functions. The memory space address listed for each
register is an offset from the base memory address programmed into the MMADR register (PCI
configuration offset 14h).
Figure 7. Graphics Controller Register Memory and I/O Map
gfx_reg_m
a
- Instruction Control Regs.
- Fence Table Registers
- Interrupt Control
Local Memory Interface
Control Registers
00000h
00FFFh
01000h
VGA and Ext. VGA RegistersVGA and Ext. VGA Registers
I/O Space Map
(Standard graphics locations)
Memory Space Map
(512 KB allocation)
Offset From
Base_Reg
Test & Diagnostic Registers
04FFFh
05000h
02FFFh
03000h
03FFFh
04000h
05FFFh
06000h
06FFFh
07000h
0FFFFh
10000h
Misc I/O Control Registers
Clock Control Registers
Reserved
1FFFFh
20000h
2FFFFh
30000h
3FFFFh
40000h
4FFFFh
50000h
5FFFFh
70000h
7FFFFh
Page Table Range
Reserved
Overlay Registers
1
Blt Engine Control Status (RO)
Reserved
- Cursor Registers
- Display Registers
- Pixel Pipe Registers
60000h
6FFFFh
- TVout Registers
- Misc Multimedia Registers
1. Some Overlay registers are
double-buffered with an additional address
range in graphics memory. See Overlay
Register Chapter for details.
Note:
MMADR Regist
e
(Base Address)
1931