User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
305
Bit Description
2:0 Error Type:
000 = Invalid Table
001 = Invalid Page table entry
010 = Incorrect target for Display surface (Request to lm if the surface started in mm or vice
versa)/Overlay surface (Request to lm).
011 = Invalid Miss during Display/Overlay accesses
100 = Illegal translation data (translation is valid and address points to PAM, SMM, over top and
other restricted spaces in main memory).
101 = Access to local memory when not present.
110 = Surface tiled in Y when not allowed (Render/Display/Overlay)
111 = Reserved
Notes:
Type 4 is reported by the main memory controller logic of the GMCH. Page Table Access done at the
main memory controller is done on a QW basis. This logic area has no concept of DW accesses, i.e. the
high or low DW page entry actually being requested. Error reporting for page entries pointing to invalid
memory ranges is therefore done for both page entries within the QW (assuming both entries are marked
valid.) If one page entry in the QW being accessed points to an illegal address, that entry is reported. If
both entries in the QW being accessed point to invalid addresses, the hardware by convention reports the
upper entry only.
When reporting page table error type 4 for addresses mapped to above top of physical memory, Page
Table Entry:
31:29 Reserved <= HW does NOT decode these bits.
28:12 Physical Address <= HW is only sensitive to these bits.
11:3 Reserved
2:1 T1T0
0 Valid
This means any addresses mapped to range ≥ 512 MB and < 4 GB will be treated by the error detection
logic as wrap around at the 512 MB boundary. Within the 512 MB block, if the address is at or above top
of physical memory (or above top of physical memory minus TSEG range if TSEG is enabled), then a
type 4 error will be generated.