User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
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16.1.5. RINGBUF—Ring Buffer Registers
Address Offset: 02030h – 0207Fh
02030h – 0203Fh: Low Priority Ring
02040h – 0204Fh: Interrupt Ring
02050h – 0205Fh: Reserved
02060h – 0207Fh: Reserved
Default Value: 00000000h
Access: Read/32 bit Write Only
Size: 4 DWords
Each Ring buffer is defined by a four DWord register set, which includes starting address, length, head
pointer, and tail pointer. The ring buffer can be disabled when empty. A driver uses two sets of ring
buffers, low priority and interrupt.
Instruction ring buffers must be located in main memory. There is no hardware support for ring buffers
that are mapped to local memory. There is neither a hardware error detection for intentional or
inadvertent attempts to map the ring buffers to local memory. This requirement applies to both low
priority and interrupt rings.
Intel
®
810 Chipset and Intel
®
815 Chipset Errata
Address Offset: 2030h–207Fh
DWord Offset 0, 1, 2, and 3
Bit 2:1 Automatic Report Head pointer. Autoreport happens on a 64K or 128K boundary. When the
head pointer crosses the ring buffer size on an autoreport boundary, the hardware erroneously reports
the head pointer address == ring buffer size, as opposed to wrapping around and reporting 0. This is an
Intel
®
810 chipset and Intel
®
815 chipset Silicon Errata. Note that the size of the ring buffer is not
restricted to a power of two.
A software work-around can be implemented as follows:
The reported head pointer should be bit-wise AND’d by the size of the ring buffer minus 1B.
For example,
ring buffer size = 128KB
HW reported head pointer = bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb B
Mask (128KB-1B) = 00000000 00000001 11111111 11111111 B
Corrected head pointer = 00000000 0000000b bbbbbbbb bbbbbbbb B
Note that this error only occurs in autoreport head mode. There is not a problem with the instruction
parser command GFXCMDPARSER_REPORT_HEAD.