User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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• VGA and Extended VGA Control Registers (00000h−
−−
−00FFFh). These registers are located in
both I/O space and memory space. The VGA and Extended VGA registers contain the following
register sets: General Control/Status, Sequencer (SRxx), Graphics Controller (GRxx), Attribute
Controller (ARxx), VGA Color Palette, and CRT Controller (CRxx) registers. Detailed bit
descriptions are provided in the VGA and Extended VGA Register Chapter. The registers within a
set are accessed using an indirect addressing mechanism as described at the beginning of each
section. Note that some of the register description sections have additional operational information
at the beginning of the section.
• Instruction, Memory, Interrupt Control, and Error Registers (01000h−
−−
−02FFFh). The
Instruction and Interrupt Control registers are located in main memory space and contain the
following types of registers:
 Instruction Control Registers. Ring Buffer registers and page table control registers are located
in this address range. Various instruction status, error, and operating registers are located in
this group of registers.
 Graphics Memory Fence Registers. The Graphics Memory Fence registers are used for
memory tiling capabilities.
 Interrupt Control/Status Registers. This register set provides interrupt control/status for various
GC functions.
 Display Interface Control Register. This register controls the FIFO watermark and provides
burst length control.
• Local Memory Registers (03000h−
−−
−03FFFh). These registers are located in main memory space
and provide local memory DRAM control.
• Reserved (04000h−
−−
−04FFFh).
• Miscellaneous I/O Control Registers (05000h−
−−
−05FFFh). This chapter provides miscellaneous I/O
control register functions.
• Clock Control Registers (06000h−
−−
−06FFFh). This memory address space is the location of the GC
clock control and power management registers.
• Reserved (07000h−
−−
−0FFFFh).
• Page Table Range (10000h−
−−
−1FFFFh).
• Reserved (20000h−
−−
−2FFFFh).
• Overlay Registers (30000h−
−−
−3FFFFh). These registers provide control of the GC overlay engine.
The overlay registers are double-buffered with one register buffer located in graphics memory and
the other on the GC chip. On-chip registers are not directly writeable. To update the on-chip
registers software writes to the register buffer area in graphics memory and instructs the GC to
update the on-chip registers.
• Blitter Status Registers (40000h−
−−
−4FFFFh). For debug purposes only, a set of read-only registers
provide visibility into the BLT engine status.
• Reserved (50000h−
−−
−5FFFFh). (Reserved in the Intel
®
815 chipset).
• LCD/TV-Out Registers (60000h−
−−
−6FFFFh). This memory address range is used for LCD/TV-Out
control registers.
• Cursor, Display, and Pixel Pipe Registers (70000h−
−−
−7FFFFh). This memory address range is
used for cursor control, display, and pixel pipe control registers.