User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
314
16.1.11. INSTPM—Instruction Parser Mode Register
Address Offset: 020C0h
Default Value: 00h
Access: Read/Write
Size: 8 bits
The bits in this register control the operation of the Instruction Parser.
Note: If an instruction type is disabled, the parser will read it out of the instruction / batch FIFO but will not
send it to its destination. Error checking will be performed.
7 6 5 4 3 2 1 0
Reserved Enable
Sync
Packet
AGP Flush
(Rsvd)
Enable
Sync
Packet
Flush
Disable
Mcomp
Instrs
Disable
GDI Blitter
Instrs
Disable
Render
(3D/Stretc
h) Instrs
Disable
State
Variable
Updates
Disable
Render
Palette
Updates
Bit Description
7 Reserved
6 Enable Sync AGP Flush. Enable pipe and AGP flush. Set by software and cleared by the parser on
detecting graphics pipe flushed before parsing a subsequent packet.
1 = Enable
0 = Cleared by graphics controller
5 Enable Sync flush. Enable pipe flush. Set by software and cleared by the parser on detecting graphics
pipe flushed before parsing a subsequent packet.
1 = Enable
0 = Cleared by graphics controller
4 Disable Mcomp Instructions. Disable processing of mcomp instructions by parser.
1 = Disable
0 = Enable
3 Disable GDI Blitter Instructions. Disable processing of Blitter instructions
1 = Disable
0 = Enable
2 Disable Render (3D/Stretch) Instructions. Disable processing of 3D instructions (Client 00h) by
parser.
1 = Disable
0 = Enable
1 Disable State Variable Updates.
1 = Disable
0 = Enable
0 Disable Render Palette Updates.
1 = Disable
0 = Enable