User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
316
Bit Description
11:10 CSDMA State Machine: Is responsible for the control of the DMA FIFO. It get requests from the
arbitration state machine. It manages the FIFO so that requests are only made when there is space in
the FIFO.
00 = DMAIDLE: Reset State - No DMA Active
01 = DMAREQ: Request State – Generate request
10 = DMAWT: Wait State - Stay in this state till space becomes available
11 = DMARWT: Wait for Acknowledge State - Stay in this state till acknowledged. Hold request
9:8 CSSW State Machine: Main Arbiter between Low Priority Ring, Interrupt Priority Ring and Batch
Buffer.
00 = SWIDLE: Reset State
01 = SWBLOCK: Assert Parser Block
10 = SWSTOP: Once Parser has gone to idle, request the dma engine to stop
11 = SWPOP: Once the DMA has gone to idle, pop the FIFO till the CSDMA indicates DMA done
7:4 CSARB State Machine: Blocks the Command Parser from parsing further and cleans up the FIFO.
0000 = ARBIDLE: Reset State – Waiting for next arbitration request
0001 = ARBLOW: Low Priority Ring Active
0010 = ARBL2ISW: Switch from Low Priority Ring to High Priority Ring. Initiated by the parser (by
masking the valid bit)
0011 = ARBLBAT: In Batch Buffer initiated from Low Priority Ring
0100 = ARBL2BSW: Switch from Low Priority Ring to Batch Buffer. Initiated by the parser
0101 = ARBINTR: Interrupt Active Ring Active
0110 = ARBI2BSW: Switch from Interrupt Ring to Batch Buffer. Initiated by the parser
0111 = ARBIBAT: In Batch Buffer initiated from Interrupt Priority Ring
1000 = ARBI2DSW: Switch from Interrupt Ring to Idle, if a wait for event packet was received (parser
masks the valid bit)
3:0 CSCPR State Machine: Command Parser.
0000 = CPRIDLE: Reset State. Parser is in Idle looking at the next header
0001 = CPRSW: When waiting for engines to go idle either for non-pipelined SVs or for engine switch
0010 = CPRHDR: Clock to get rid of header when not loaded externally
0011 = CPRCMD: Command State that have data/address to load
0100 = CPREVT: For some Parser events like WT4EVT packet, brekapoint interrupt
0101 = CPRFLSH: If all engines are done, request for Local Cache to flush itself
0110 = CPRSTDA: Store DWord Address (report head command also)
0111 = CPRSTDW: Store DWord Data
1000 = CPRHLD1: Hold address/data for external interface. For internal interface just mimic external
interface
1001 = CPRHLD2: Hold Address and Data for one more clock
1010 = CPRWT: Wait State
1011 = CPRPOPA: If fast load
1100 = CPRPOPB: If fast load