User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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16.1.13. BBP_PTR—Batch Buffer Parser Pointer Register (debug)
Address Offset: 020C8h
Default Value: 00000000h
Access: Read Only
Size: 32 bits
This register contains the offset from the batch buffer start address of the DWord being parsed by the
Instruction Parser.
31 19 18 2 1 0
Reserved Address Offset Reserved
Bit Description
31:19 Reserved
18:2 Batch Buffer Address Pointer Offset.
1:0 Reserved
16.1.14. ABB_STR—Active Batch Buffer Start Address Register (debug)
Address Offset: 020CCh
Default Value: 00000000h
Access: Read Only
Size: 32 bits
This register is loaded with the start address of the Batch Buffer request.
The ABB_STR and ABB_END Registers will not get loaded if they are popped off of the stack. This can
occur if a low priority ring batch buffer is interrupted at a chain point by Interrupt Priority ring execution
and then is later continued. The Start and End addresses for the low priority ring chain portion that was
interrupted will not be stored in the ABB_STR and ABB_END Registers. This is an operational anomaly
that will not be corrected.
31 26 25 3 2 1 0
Reserved Batch Buffer Request Start Address Reserved Source of the
Batch buffer
Bit Description
31:26 Reserved
25:3 Batch Buffer Request Start Address.
2 Reserved
1:0 Source of the Batch Buffer.
00 = Low Priority Ring
01 = Interrrupt Ring
1X = Reserved