User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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3.2. GC Register Memory Address Map
All GC registers are memory-mapped. In addition, the VGA and Extended VGA registers are I/O
mapped.
Table 2. Memory-Mapped Registers
Address Offset Symbol Register Name Access
00000h−00FFFh  VGA and VGA Extended Registers
These registers are both memory and I/O mapped
and are listed in the following table. Note that the I/O
address and memory offset address are the same
value for each register.

Instruction and Interrupt Control Registers (01000h−
−−
−02FFFh)
01000h−01FFFh  Reserved. Do not write 
02000h−0201Fh FENCE[0:7] Graphics Memory Fence Table Register [0:7] R/W
02020h−02023h PGTBL_CTL Page Table Control Register R/W
02024h−02027h PGTBL_ER Page Table Error Register RO
02028h−0202Bh PGTBL_ERRMSK Page Table Error Mask Register R/W
02030h–0207Fh
02030h–0203Fh
02040h–0204Fh
02050h–0207Fh
RINGBUF Ring Buffer Registers
Low Priority Ring Buffer (4 DWs)
Interrupt Ring Buffer (4 DWs)
Reserved
R/W
02080h–02083h HWS_PGA Hardware Status Page Address Register R/W
02084h–02087h  Reserved 
02088h–0208Bh IPEIR Instruction Parser Error Identification Register RO
0208Ch–0208Fh IPEHR Instruction Parser Error Header Register RO
02090h–02091h INSTDONE Instruction Stream Interface Done Register RO
02092h–02093h  Reserved 
02094h–02097h NOPID NOP Identification Register RO
02098h−002099h HWSTAM Hardware Status Mask Register R/W
0209Ah–0209Fh  Reserved 
020A0h−020A1h IER Interrupt Enable Register R/W
020A2h–020A3h  Reserved 
020A4h−020A5h IIR Interrupt Identity Register R/WC
020A6h–020A7h  Reserved 
020A8h−020A9h IMR Interrupt Mask Register R/W
020AAh–020ABh  Reserved 
020ACh−020ADh ISR Interrupt Status Register RO
020AEh−020AFh  Reserved 
020B0h−020B1h EIR Error Identity Register R/WC
020B2h−020B3h  Reserved 
020B4h−020B5h EMR Error Mask Register R/W
020B6h−020B7h  Reserved 
020B8h−020B9h ESR Error Status Register RO
020BAh−020BFh  Reserved 