User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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16.2.1. HWSTAM—Hardware Status Mask Register
Address Offset: 02098h
Default Value: FFFFh
Access: Read/Write
Size: 16 bits
This register has the same format as the Interrupt Control Registers. The corresponding bits are the mask
bits that prevent that bit in the Interrupt Status Register from generating a PCI write cycle. Any
unmasked interrupt bit (set to 0) will allow the Interrupt Status Register to be written to the address
specified by the Hardware Status Vector Address Register when the Interrupt Status Register changes
state.
15 14 13 12 11 10 9 8
HW
Detect
Error
Master
Reserved Sync
Status
Toggle
Pri Dply
Flip
Pending
Reserved Overlay 0
Flip
Pending
Reserved
7 6 5 4 3 2 1 0
Pri Dply
VBLANK.
Pri Dply
Event
Reserved Reserved Reserved Reserved User
Defined
Interrupt
Breakpoint
Bit Description
15:0 Interrupt Status Mask Bits.
0 = Not Masked.
1 = Masked (prevents PCI write cycle.).