User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
325
16.2.4. IMR—Interrupt Mask Register
Address Offset: 020A8h
Default Value: FFFFh
Access: Read/Write
Size: 16 bits
An interrupt that is masked by this register will not appear in the Interrupt Identity Register and will not
generate an interrupt.
15 14 13 12 11 10 9 8
HW
Detect
Error
Master
Reserved Sync
Status
Toggle
Pri Dply
Flip
Pending
Reserved Overlay 0
Flip
Pending
Reserved
7 6 5 4 3 2 1 0
Pri Dply
VBLANK.
Pri Dply
Event
Reserved Reserved Reserved Reserved User
Defined
Interrupt
Breakpoint
Bit Description
15:0 Interrupt Mask Bits. See. Table 17
0 = Not Masked
1 = Masked