User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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17.3. HSYNC—Horizontal Sync Register

Address Offset: 60008h

Default Value: 00000000h

Access: Read/Write

Size: 32 bits

31 28 27 16

Reserved Horizontal Sync End

15 12 11 0

Reserved Horizontal Sync Start

Bit Description

31:28 Reserved.

27:16 Horizontal Sync End. Horizontal sync end expressed in terms of absolute pixel number relative to the

horizontal active display start.

Notes:

1. Minimum HSYNC width is 1 pixel clock.

1. An asserted HSYNC will be cleared as soon as HTOTAL end is reached, regardless of the value in

the HSYNC End register.

15:12 Reserved.

11:0 Horizontal Sync Start. Horizontal sync start expressed in terms of absolute pixel number relative to

the horizontal active display start.

Note that when HSYNC Start is programmed equal to HBLANK Start, both HSYNC and HBLANK will

be asserted on the same pixel clock.